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RMo2D-1 W-Band Noise Characterization with Back-Gate Effects for Advanced 22nm FDSOI mm-Wave MOSFETs #

Q. H. Le#* , D. K. Huynh#* , D. Wang# , Z. Zhao$, S. Lehmann$, T. Kämpfe# , M. Rudolph* CMOS Integrated RF & AI, Fraunhofer Institute for Photonic Microsystems (IPMS), Dresden, Germany * Ulrich-L.-Rohde Chair of Radio Frequency and Microwave Techniques, Brandenburg University of Technology, Cottbus, Germany $ GlobalFoundries, Dresden, Germany

Abstract — This paper presents the W-band noise performance of the 22nm FDSOI CMOS technology. In detail, the mm-wave thin-oxide MOSFETs is characterized comprehensively in term of device geometries using the tuner-based noise measurement approach. To aid the noise analysis and extraction, the following study adopts an accurate small-signal equivalent circuit model validated well with bias-dependence up to 110 GHz. The effects of back-gate bias to the overall noise performance are also addressed in this work. The test devices exhibit low noise figure in the full W-band 75-110 GHz. Besides, NFmin of 2.8 dB and 3.6 dB is recorded at 94 GHz respectively for the n- and p-FETs with 18nm gate-length (Nf = 32, Wf = 1.0 µm). The result of this study indicates the comparable performance of the 22nm FDSOI technology to other candidates for W-band applications. Keywords — 22FDX® , FDSOI, CMOS, W-band, small-signal model, thermal noise, automotive radar.

Fig. 1. Cross section of the thin-oxide n- and p-MOSFETs in 22nm FDSOI technology with flip well architecture.

I. I NTRODUCTION The W-band (75-110 GHz) has long been reserved for mm-wave radar and satellite communications. On the other hand, the rapid advancement of the telecommunications technology raises the need for higher data transmission capacity that extends its operating zone to the mm-wave regime. Hence, further W-band spectrum allocations have been defined, especially when the automotive industry is also migrating from the conventional 24 GHz band to the upper 77/79 GHz for more bandwidth. At such high frequencies SiGe heterojunction bipolar transistors (HBTs) or III-V high electron mobility transistors (HEMTs) have been dominating the radio frequency integrated circuit (RFIC) market for decades while planar silicon CMOS was still under continuous development to meet the market demand. In addition, the use of Si-based CMOS is not common in this specific field due to performance and reliability issues. With the introduction of the latest 22nm fully-depleted silicon-on-insulator (FDSOI) technology, extended cut-off frequency over 350 GHz and high performance spanning along the sub-110 GHz range are recorded for planar CMOS [1]–[4]. The advanced FDSOI technology has been recognized as a potential candidate for the design community as being an optimal and cost-effective solution for modern low-power RFICs. In a wireless receiver chain, a low-noise amplifier (LNA) plays an important role in maintaining signal integrity. As for LNA design, the achievable noise performance is dictated by the core transistor technology. A recently reported LNA

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in 22nm FDSOI technology, for instance, achieves very low noise figure (NF) of 1.46 dB at 28 GHz [4]. This work thereby investigates particularly the high frequency noise characteristics of the 22nm FDSOI transistors for W-band applications. The test structures consist of the thin-oxide nand p-MOSFETs fabricated in GlobalFoundries’s 22FDX® process. A variety of device geometries with gate-length (lg ) from 18 nm to 40 nm and finger-width (Wf ) of 1 µm and 5 µm are available for the following study. The technology platform also offers devices with flip-well architectures optimized for forward back-gate biasing (see Fig. 1). In addition, the transistors used in this work are in common-source configuration and embedded in a 2-port test fixture with 50µm pitch ground-signal-ground (GSG) pattern. At first stage, S-parameters up to 110 GHz are characterized to construct the small-signal model for the noise analysis. The four noise parameters are then determined in the full W-band 75-110 GHz using a tuner-based measurement setup. The noise sources and their correlation at the device intrinsic plane are also extracted. The effects of back-gate bias to the W-band noise performance are investigated in the last stage. II. DC A NALYSIS AND RF S MALL -S IGNAL M ODEL The DC characteristics of the device under test (DUT) are firstly examined from experimental data and the BSIM-IMG core model provided by foundry’s process design kit (PDK). The IV curves, current density and transconductance of a 32-finger (Nf = 32) n-FET with lg = 18 nm, Wf = 1 µm are shown in Fig. 2. The good agreement between simulation and measurement validates the core model for further DC assessments. The maximum transconductance is recorded at the corresponding current density of 0.5 mA/µm for the concerned device.

2020 IEEE Radio Frequency Integrated Circuits Symposium

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(a) (b) Fig. 2. (a) IV curves, (b) current density and transconductance of the 32×1.0µm n-FET (lg = 18 nm) between simulation and measurement.

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(c) (d) Fig. 4. (a, b) Y-parameters, (c) S-parameters and (d) maximum gain (MSG/MAG) between measurement (blue symbol) and simulation (red solid line) at VDS = 0.8 V of the 32×1.0µm n-FET (lg = 18 nm).

Fig. 3. MOSFET small-signal model including noise sources.

The small-signal equivalent circuit adopted in this work is illustrated in Fig. 3. The non-quasi static effect is addressed by the intrinsic resistances Rgs , Rgd and the complex transconductance gm with a time delay τ . The extrinsic series source/drain resistances Rs , Rd , furthermore, are bias-dependent to account for the overlap area between the gate and the highly doped source/drain regions. 2-port S-parameters are measured from 100 MHz to 110 GHz using a vector network analyzer (VNA) Keysight PNA-X N5247B calibrated with Line-Reflect-Reflect-Match (LRRM) technique. The measurement results are subsequently de-embedded by using dedicated open-short structures to remove the fixture parasitics down to the first metal layer. The extrinsic parameters are determined under cold conditions (VDS = 0 V) as explained in [5]. The gate resistance, series inductances and substrate parasitics are found in depletion region. The bias-dependent Rs and Rd are extracted in strong inversion region at different gate-biases. The intrinsic elements are then determined with Y-parameters after removing the extrinsic parts. Fig. 4 demonstrates the Y- and S-parameters of the 32-finger n-FET (lg = 18 nm, Wf = 1 µm) at different bias conditions. The simulation and measurement results are in good agreement with each other across the whole bandwidth. Moreover, the well-predicted maximum attainable gains consolidate the model accuracy. Regarding the high frequency noise analysis, the noise contribution from the series resistances are calculated from the thermal noise formula [4]. Besides, two correlated noise sources at the intrinsic plane are implemented following the approach described in [6]. In detail, i2g and i2d represent respectively the induced gate noise and channel thermal noise while their correlation is denoted as ig i∗d . The above validated model serves as a means to extract the noise power spectral densities discussed in the next section.

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III. W-B AND N OISE C HARACTERIZATION A. Measurement setup and calibration Diagram of the W-band noise measurement system is shown in Fig. 5. The PNA-X with frequency extenders is used to measure 2-port S-parameters of the DUT at first stage. A calibrated noise source ELVA-1 ISSN-10 and an automated impedance tuner MT979A from Maury Microwave locate at input side of the DUT are used to measure the four noise parameters in the 75-110 GHz frequency range. To improve the receiver sensitivity, the output signal is amplified and then downconverted before being fed to the built-in noise receiver of the VNA. Besides, a source measure unit (SMU) Keysight B2902B supplies the DC voltages for the DUT while monitoring the gate and drain currents. An in-situ calibration consisting of two separate vector calibrations is performed prior to the measurement at room temperature. In particular, a 2-port calibration is firstly applied at the probe-tip plane using LRRM technique on an impedance standard substrate. A 1-port Open-Short-Load (OSL) calibration is performed subsequently at the noise source reference plane while the probes are still being placed on the thru structure. Through this approach, the noise source and tuner can be characterized directly in the fully assembled system. The noise receiver calibration is carried out as the final step. In addition, the measurement is performed using cold-source technique and the results are de-embedded to the first metal with dedicated open-short structures. B. Device characterization As for the first demonstration, the 32×1.0µm n-FET with 18nm gate-length is characterized at different operating points. The equivalent circuit model in previous section is applied for the extraction of the noise sources. The intrinsic noise

Fig. 5. W-band noise parameter measurement setup.

sources and their correlation are obtained after removing the extrinsic parameters by applying the method in [6]. Besides, the analysis is performed based on the median of 7 measured dies. The extracted noise sources are then fitted back into the model for verification. Fig. 6 illustrates the measurement and simulation results at different gate biases. The simulation and measurement results are in good agreement with each other. The test transistor in general exhibits low NFmin and low Rn in the full W-band. Very low NFmin of 2.5-3.3 dB is particularly observed from 90 to 110 GHz. The extracted noise sources versus frequency and gate-bias are depicted in Fig. 7.

(a) (b) Fig. 8. NFmin and normalized Rn versus current density at (a) 79 GHz and (b) 94 GHz of the 32×1.0µm n- and p-FETs (lg = 18 nm).

Fig. 9. NFmin at 94 GHz of the 32×1.0µm n- and p-FETs with different gate lengths measured at a current density of about 250 mA/µm.

In addition, the minimum noise figure and the equivalent noise resistance in term of current density of the 32×1.0µm nand p-FETs (lg = 18 nm) at 79 GHz and 94 GHz are illustrated in Fig. 8. The NFmin measured at 94 GHz for devices with different channel lengths is shown in Fig. 9. As observed from the graphs, both n- and p-FETs feature low noise figure at the W-band frequencies. IV. A NALYSIS OF BACK - GATE BIAS EFFECTS (a) (b) Fig. 6. NFmin and normalized Rn versus frequency between measurement (grey symbol line) and simulation (blue solid line) of the 32×1.0µm n-FET (lg = 18 nm) at VDS = 0.8 V.

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(b) Fig. 7. Extracted noise sources and their correlation of the 32×1.0µm n-FET (lg = 18 nm) in term of (a) frequency and (b) gate-source voltage.

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A recent study on the back-gate bias effects to the RF and noise performance of the 22nm FDSOI transistors has been conducted in [3] at lower frequencies. This part accordingly extends the analysis into the 75-110 GHz frequency range. A 16×5.0µm n-FET (lg = 18 nm) with an n-well is used to study the effect of back-gate bias to the W-band noise characteristics. The device is embedded in a specific 3-port test structure which the third port is only for supplying the back-gate voltage. Fig. 10 shows the noise performance versus VGS for different back-gate biases at 79 GHz and 94 GHz. Besides, the drain and gate currents monitored during the measurement are depicted in Fig. 11. It can be observed that the noise characteristics are shifted with respect to the applied forward VBS . This results from the adjustment of the threshold voltage which shifts the drain current characteristics. Unlike what mentioned in [7] that the forward back-gate bias worsens the noise performance, the measured data reveal no negative impact from the back-gate bias but only a shift in the overall behaviour. This is also in good agreement with the results reported in [3] even at this high frequency range. Furthermore, by operating the device at lower VGS , the vertical field is reduced which lowers the gate-leakage current. The back-gate bias is, therefore, useful for ultra-low-voltage operation.

Table 1. Recorded noise performance at 94 GHz of different mm-wave transistor technologies.

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Reference 2008 [8] 2011 [9] 2009 [10] 2011 [11] 2003 [12] This work

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Technology 65nm CMOS 45nm CMOS SiGe HBT SiGe HBT InP HEMT 22nm FDSOI

NFmin [dB] 5 4.6 3.2 2.5 2.1 2.8

Rn [Ω] 60 35 15.5 20 20 31

NFmin of 2.8/3.6 dB is measured for the 18nm gate-length n-/p-FETs at 94 GHz. The advanced planar FDSOI CMOS shows comparable noise performance to other technologies such as SiGe HBT or HEMT for W-band applications. The back-biasing capability, moreover, enables flexibility in performance control that is beneficial for low-power RFICs. ACKNOWLEDGMENT The authors would like to thank GlobalFoundries Dresden for providing the test structures. The authors from Fraunhofer IPMS would particularly like to thank Remi Tuijtelaars from bsw TestSystems & Consulting for his valuable support in the noise measurement setup. This work is funded by project OCEAN12 from the ECSEL Joint Undertaking and project WIN FDSOI from IPCEI.

(c) (d) Fig. 10. (a, b) NFmin and (c, d) rn of the 16×5.0µm n-FET (lg = 18 nm) in term of back-gate bias.

R EFERENCES

(a) (b) Fig. 11. Drain and gate currents of the 16×5.0µm n-FET (lg = 18 nm) monitored during the noise measurement in term of back-gate bias.

V. D ISCUSSION Table I lists the recorded noise performance at 94 GHz of various device technologies. According to the results the 22nm FDSOI technology outperforms its bulk CMOS counterparts with lower minimum noise figure and equivalent noise resistance. On the other hand, the noise characteristics are comparable to SiGe HBT and HEMT in this frequency range. The significant improvement on the p-channel devices also provides an alternative choice for circuit design. As presented in [2], the 22nm FDSOI transistors demonstrate reliable RF operation even when being driven into strong compression and at excess drain voltage. This technology, furthermore, has the advantage of the back-gate bias allowing better control and tuning of performance. With such features, the 22nm FDSOI technology is proven to be a potential candidate for automotive and mm-wave radar applications in which high performance and reliability are required. VI. C ONCLUSION This paper demonstrates the state-of-the-art W-band noise performance of the 22nm FDSOI technology. The study is also conducted in term of device geometry and back-gate bias effects. Low NFmin and Rn are recorded for both n-/p-FETs in the frequency range 75-110 GHz. In particular,

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[1] R. Carter et al., “22nm FDSOI technology for emerging mobile, internet-of-things, and RF applications,” in Proc. IEEE International Electron Devices Meeting (IEDM), Dec. 2016. [2] Q. H. Le et al., “DC-110 GHz characterization of 22FDX® FDSOI transistors for 5G transmitter front-end,” in Proc. 49th European Solid-State Device Research Conference, Sep. 2019. [3] S. N. Ong et al., “22nm FD-SOI technology with back-biasing capability offers excellent performance for enabling efficient, ultra-low power analog and RF/millimeter-wave designs,” in Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Jun. 2019. [4] L. H. K. Chan et al., “22nm fully-depleted SOI high frequency noise modeling up to 90GHz enabling ultra low noise millimetre-wave LNA design,” in Proc. IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Jun. 2019. [5] Q. H. Le et al., “Small-signal modeling of mm-wave MOSFET up to 110 GHz in 22nm FDSOI technology,” in Proc. Asia-Pacific Microwave Conference (APMC), Dec. 2019. [6] G. Knoblinger, “RF-noise of deep-submicron MOSFETs: Extraction and modeling,” in Proc. 31st European Solid-State Device Research Conference. IEEE, 2001. [7] P. Kushwaha et al., “Characterization of RF noise in UTBB FD-SOI MOSFET,” IEEE Jour. Electron Devices Society, vol. 4, no. 6, pp. 379–386, Nov. 2016. [8] N. Waldhoff et al., “Small signal and noise equivalent circuit for CMOS 65 nm up to 110 GHz,” in Proc. 38th European Microwave Conference, Oct. 2008. [9] L. Poulain et al., “Small signal and HF noise performance of 45 nm CMOS technology in mmW range,” in Proc. IEEE Radio Frequency Integrated Circuits Symposium, Jun. 2011. [10] Y. Tagro et al., “In-situ silicon integrated tuner for automated on-wafer MMW noise parameters extraction using multi-impedance method for transistor characterization,” in Proc. 2009 IEEE International Conference on Microelectronic Test Structures, Mar. 2009. [11] K. H. Yau et al., “Characterization of the noise parameters of SiGe HBTs in the 70–170-GHz range,” IEEE Trans. on Microwave Theory and Techniques, vol. 59, no. 8, pp. 1983–2000, Aug. 2011. [12] T. Vaha-Heikkila et al., “On-wafer noise-parameter measurements at W-band,” IEEE Trans. Microwave Theory and Techniques, vol. 51, no. 6, pp. 1621–1628, Jun. 2003....