Divide by 3 counter design PDF

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Summary

Solution explaining the design of clock divider circuit...

Description

Q. Design a clock divider circuit which divides the clock by an odd number and has 50% duty cycle. (o/p clk = i/p clk /N, where N is an odd number). Sol: We will first examine an example where the input clock is divided by 3. After, which we will generalize the steps for any odd number. Step I : Design a odd number counter (in this case, counter which counts up-to 2) State Diagram:

State Table:

K-MAP

Logic Circuit:

Waveform:

Step II : 50% duty cycle Now, we have divided the input clock by 3, but the duty cycle is still not 50%. To get 50% duty cycle, we shift the Q0 output by 90 degrees and add a gate to OR the two flip flops' output.

The above method can be extended to other odd larger by divide "N" numbers by following the same design flow :

 Design a Up or Down divide by "N" counter.  Add a flip flop to follow one of the flip flops in the counter 1/2 clock cycle.  OR the output of added flip flop with the one that is driving it to achieve 50% duty cycle....