ECE 2000 2 Fall 2021 sol1 PDF

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Solution for HW1...

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Solution Set 1 In the following circuits (Figs. 1 and 2), assume that all devices have |VT h | = 2 V and exhibit |ID(sat) | = 2 mA when |VGS | = 3 V. 1. Solve for the drain current ID for the MOSFET in Fig. (1) 2. Solve for the drain current ID for the MOSFET in Fig. (2)

Fig. (1)

Fig. (2)

Solution: 1. This circuit contains an NMOS transistor. Define the positive supply voltage to be VDD and the negative supply voltage to be VSS . From Fig. (1), we know that VDD =5 V and VSS = −5 V. First we need to find the NMOS gate voltage VG using voltage division. 4 MΩ (VDD − VSS ) + VSS ) 4 MΩ + 1 MΩ 4 = (5 − (−5)) + (−5) = 3 V 4+1

VG =

Apply KVL at the gate source loop: (This loop starts from the gate voltage VG , then has a potential drop across the gate to source VGS , then another potential

drop across the 125 Ω resistor, and finally ends at the negative supply Vss) VG − VGS − 125 Ω(ID ) = V ss VG − VGS − 125(ID ) = −5 VG = VGS + 125(ID ) − 5 VGS + 125ID = 8 We do not know what region of operation the transistor is in, so we have to make an assumption at the beginning. We often first assume that the transistor is in saturation, since the saturation region ID equation has fewer unknown variables than the linear region ID equation. Assuming saturation, the drain current is given by ID =

kn (VGS − VT h )2 2

Substitute ID into the KVL gate source loop equation that we obtained earlier:   kn 2 (VGS − VT h ) = 8 VGS + 125 2 We know VT h = 2 V from the information given in the problem. We can solve for kn using the other information provided. Since we are given a specific drain current value at a specific gate to source voltage when the transistor is in saturation (ID(sat) = 2 mA at VGS = 3 V), we find kn (VGS − VT h )2 2 2ID(sat) 2(2mA) kn = = 2 (3V − 2V )2 (VGS − VT h ) A mA kn = 4 2 = 4 × 10−3 2 V V ID(sat) =

Plug-in kn and VT h values.  kn 2 (VGS − 2) = 8 VGS + 125 2 2VGS + 125(4 × 10−3 (VGS − 2)2 ) = 16 2 2VGS + 0.5(VGS − 4VGS + 4) = 16 

2 0.5VGS = 14 2 VGS = 28

VGS = ±5.29 V We choose positive VGS since that value satisfies the MOSFET on condition: VGS > VT h .

Plug-in VGS into saturation region equation to solve for drain current ID . (Note that this current value we obtain needs to be checked to make sure that it does not violate the saturation region condition) kn (VGS − VT h )2 2 4mA/V 2 (5.29 V − 2 V)2 ID = 2 ID = 2(3.29)2 mA ID =

From the above we find that ID = 21.64 mA= 21.6×10−3 A. To verify our answer, apply KVL at the drain source loop: (This loop starts from the positive voltage source VDD , then has a potential drop across the 250 Ω resistor, drain to source VDS , the 125 Ω resistor, and finally ends at the negative supply VSS ) VDD − (ID )250 − VDS − 125(ID ) = VSS VDD = (ID )250 + VDS + 125(ID ) + VSS 5 V = (21.6 × 10−3 )250 + VDS + 125(21.6 × 10−3 ) − 5 V VDS = 1.9 V We now need to see if this value is greater than the minimum value of VDS , which we will define as VDS(sat) required to satisfy the saturation region condition. VDS (sat) = VGS − VT h = 3.3 V VDS < (VDS (sat) ) Clearly, the VDS is smaller than the minimum value required for the transistor to be in saturation. This violates our assumption, and therefore we resolve for ID again in a different region. This time, we assume that the transistor’s region of operation is Linear/Triode: We go back to the KVL at the gate source loop equation, and now we plug-in ID equation for the linear region:   1 2 VGS + 125 kn ((VGS − VT h )VDS − VDS ) = 8 2   1 2 −3 VGS + 125 4 × 10 ((VGS − VT h )VDS − VDS ) = 8 2   1 2 VGS + 0.5 ((VGS − VT h )VDS − VDS ) = 8 2

However, we now have 2 unknowns: VGS and VDS . We need more equations to solve for both unknowns. We develop an equation by applying KVL at the drain source loop equation to obtain: VDD − (ID )250 − VDS − 125(ID ) = VSS 10 V = (ID )250 + VDS + 125(ID ) VDS = 10 − 375ID We modify the KVL at the gate source loop equation by using the VG value we obtained from the beginning: VG − VGS − 125 Ω(ID ) = VSS VGS = 8 − 125ID Solving the above two equations (VDS and VGS ) gives us: VDS − 3VGS = −14 VDS = 3VGS − 14 Plugging in VDS to the earlier equation (The gate source loop KVL with the linear region ID equation plugged in) gives us:   1 2 VGS + 0.5 (VGS − 2)(3VGS − 14) − (3VGS − 14) = 8 2 2 −3VGS + 48VGS − 140 = 32 2 −3VGS + 48VGS = 172 2 3VGS − 48VGS + 172 = 0 ∴ VGS = 5.42 V or 10.58 V

We check the first solution VGS = 5.42 V and VDS = 2.26 V. This satisfies VDS < VDS (sat) to show the device operates in Linear region. ID = (10 − VDS )/375 = 20.64 mA. The final operating point of this transistor is (VDS , ID ) = (2.26 V, 20.64 mA). 2. This circuit contains a PMOS transistor. Similarly, positive supply voltage VDD = 5 V and the negative supply voltage VSS = −5. We find VG by voltage division between the 350 Ω and the 1000 Ω resistors. VG =

350 (5 − (−5)) − 5 = −1.5V 1000

We then do KVL for the gate source loop. (This loop is slightly different from problem 1, because the transistor is a PMOS, which means that the source is connected to the 1 kΩ resistor to VDD .) VG − VGS + (1000 Ω)ID = 5 V −VGS + 1000ID = 6.5 V We go through a similar process to problem 1, where we assume saturation for the PMOS transistor and plug in the saturation region ID equation into the KVL gate source loop equation. Note that the saturation current equation is negative because PMOS’s current flow is in the opposite direction compared to NMOS.   kp 2 VGS − 1000 (VGS − VT h ) = −6.5 2 The kp value is computed in a similar way to problem 1a with the exception that ID(sat) , VGS and VT h are now negative due to the transistor being a PMOS, and we would obtain kp = 4 mA/V2 and VT h = −2V for PMOS. We now solve for VGS VGS − 2(VGS + 2)2 = −6.5 2 VGS − 2(V GS + 4VGS + 4) = −6.5 2 −2VGS − 7VGS − 1.5 = 0

This yields VGS = −0.2293 V or − 3.2707 V We choose VGS = −3.2707 to satisfy VGS < VT h from the earlier equation. This gives us ID = −3.23 mA. To verify, we apply KVL at source drain loop (The loop equation is slightly different due to the transistor being a PMOS, but is mostly the same as the one in problem 1): 5 = −(−3.23 × 10−3 )103 − VDS − (−3.23 × 10−3 )2 × 103 − 5 VDS = −0.4 V

The maximum VDS for the PMOS is, VDS (sat) = VGS − VT h = −3.2707 + 2 VDS (sat) = −1.2707 V VDS > V DS (sat)

This violates saturation condition. Therefore, we are in Linear mode of operation. We now plug-in PMOS linear region ID equation to the earlier KVL gate source loop equation:   1 2 VGS + 1000 −(kp (VGS − VT h )VDS − VDS ) = −6.5 2   1 2 VGS − 4 (VGS + 2)VDS − VDS = −6.5 2 We obtain two new equations (equation 1: KVL for source to drain loop in terms of drain current and equation 2: KVL for gate to source loop in terms of drain current) in a similar way to what we did in problem 1: VDS = 3000ID − 10 VGS = 1000ID − 6.5

Solving these we get: VDS = 3VGS + 9.5 Apply VDS into the earlier equation:   1 2 VGS = −4 (VGS + 2)(3VGS + 9.5) − (3VGS + 9.5) = −6.5 2 2 6VGS + 53VGS + 111 = 0 VGS = −3.4132 or − 5.4201 VGS = −3.4132 gives VDS = −0.7396 V VDS (sat) = VGS − VT h = −1.4132 V The VDS > VDS(sat) condition is satisfied to show that the device operates in Linear region.   VDS + 10 ID = = 3.09 mA 3000 q-point: (−0.7936 V, 3.09 mA).

In the following circuits (Figs. 3 and 4), assume that |VT h | = 1 V and |ID(sat) | = 1 mA when |VGS | = 3V . For problems 3a, 3b, 4a, and 4b, the transistors MUST have a drain current of 3 mA (|ID | = 3 mA). 3a. Design Fig. 3 circuit (i.e., Compute appropriate resistor values based on the drain current and supply values). 3b. For Fig. 3 circuit, if R1 = 10 kΩ, RSS = 500 Ω, and the transistor is known to be operating in the saturation region, what is the value of R2 ? 4a. Design Fig. 4 circuit (i.e., Compute appropriate resistor values based on the drain current and supply values). 4b. For Fig. 4 circuit, if RSS = 500 Ω, what is the largest RD value that will allow the transistor to still operate in the saturation regime?

Fig. (3)

Fig. (4)

Solution: 3. First, we solve for kp using the given information: 2ID(sat) (VGS − VT h )2 mA kp = 0.5 2 V

kp =

For the design of problem 3a, you can either use the linear or saturation region current equation and plug-in the required current of −3 mA (it is negative because it is a PMOS transistor). For this design, we will follow the specifications laid out for problem 3b, which is that the PMOS transistor is in saturation. Thus, kp (VGS − VT h )2 2 3 × 10−3 = 0.5 × 10−3 /2(VGS + 1)2 VGS = 2.4641 V or − 4.4641 V We have to satisfy this inequality VGS < VT h in order for the PMOS transistor to be on. ID =

Thus, we select the negative gate to source voltage to satisfy this: VGS = −4.4641 VG − VS = −4.4641 We now apply KVL from the transistor source node voltage VS across RSS to the positive supply voltage of 3 V: VS = 3 − ID RSS If you are doing problem 3a, you are free to select the RSS value, but for problem 3b we are given: RSS = 500 Ω VS = 1.5 V VG = −2.9641 V For problem 3a, we can solve for RD by applying KVL to source drain loop (Note: VDS is opposite sign in KVL, because we are going from source to drain in KVL

loop): VDD − ID RSS + VDS − ID RD = VSS 3 = ID RSS − VDS + ID RD − 3 ID (RD + RSS ) − VDS = 6 We choose RD = 100 Ω We now have to check if the VDS value is within the saturation region limits VDS = −4.2V VDS (sat) = VGS − VT h = −3.4641V VDS < V DS (sat) ∴ Satisfying our assumption. Now, we need to determine our R1 and R2 values. Apply voltage divider at the gate node: R2 −3 VG = 6 R1 + R2 0.0359(R1 + R2 ) = 6R2 R1 + R2 = 167R2 R1 = 166R2 For problem 3a, you may select any R1 and R2 that satisfy the above equation. For problem 3b, you are given R1 so solve for R2 . R1 = 10 kΩ, R2 = 10 kΩ/166 = 60.2 Ω Hence the design values for problem 3a using the restrictions given in problem 3b are: R1 = 10 kΩ, R2 = 60.2 Ω RSS = 500 Ω, RD = 100 Ω 4. First, we solve for kn using the given information. Note: VT h is negative, but VGS is positive for a depletion mode NMOS. 2ID(sat) kn = (VGS − VT h )2 2 mA kn = (3 − (−1))2 VT h = −1 V mA kn = 0.125 2 V

For the design of problem 4a, we will follow the specifications laid out for problem 4b, which is that the NMOS is in saturation. Thus, kn (VGS − VT h )2 2 0.125 3 × 10−3 = × 10−3 (VGS + 1)2 2 VGS = 5.928 V or − 7.928 V ID =

We choose VGS = 5.928 > VT h to conduct VG − VS = 5.928 VS = ID RSS For problem 4a, you can feel free to select the RSS value, but for problem 4b, we are given: RSS = 500 Ω = 0.5 kΩ VS = 3 mA ∗ 0.5 kΩ = 1.5 V VG = 7.428 V Applying KVL at drain source loop, we get: 10 = ID RD + VDS + ID RSS ID (RD + RSS ) + VDS = 10 We need to choose a RD value so that the transistor stays in saturation. For problem 4b, we must find the largest value possible. We calculate the smallest VDS that will keep the transistor in saturation. VDS (sat) = VGS − VT h = 6.928 V 3 mA(RD + 0.5 kΩ) + 6.928 V = 10 V RD = 524 Ω which is the largest resistance. Note: In the homework submissions answer, I stated 523 Ω in case that people rounded their answers differently. For problem 4a, we finish up the rest of the resistance calculations. Using voltage division for the gate node, we have: R2 R1 + R2 7.428(R1 + R2 ) = 10R2 R1 + R2 = 1.346R2 R1 = 0.346R2 VG = 10

Thus we choose R2 = 10 kΩ, R1 = 3.46 kΩ

5. Refer to Fig. 5. This is an NMOS inverter circuit. The transistor, M1 , has VT h = 2 V. Determine the required value of kn for VOU T = 1 V when VIN = 5 V.

Fig. (5)

Solution: 5. We first solve for the drain current ID . For VOU T = 1 V we have a 4 V drop over 10 kΩ. So: ID =

VDD − VOU T = 4 V/10 kΩ 10 kΩ ID = 0.4 mA

We check for the transistor’s operating region by finding VDS and VGS : VDS = VOU T = 1V when VGS = VIN = 5V Since VGS > VT h and VDS < VGS − VT h Transistor operates in LINEAR REGION Now, use the linear region drain current equation and plug-in VDS , VGS , and VT h values

  2 VDS ID = kn (VGS − VT h )VDS − 2   2 1 0.4 mA = k (5 − 2)(1) − 2   1 = 2.5k = k 3− 2 0.4 mA k= 2.5 V2 mA ∴ k = 0.16 2 V

Refer to Fig. 6 for problems 6a and 6b. This circuit depicts a depletion mode MOSFET , |VT h | = 2 V. in the depletion load configuration. Given kn = 1 mA V2 6a. Plot ID as a function of V + over the range 0 − 10 V. Label the operating regimes of the transistor under different V + values. 6b. What operating regime is the transistor in when V + = 0.1 V

Fig. (6)

Solution: 6a. For depletion mode MOSFET, threshold voltage is negative. VT h = −2 V. From the circuit diagram, the gate and source or the MOSFET are shorted together: VGS = 0 V. This means that as long as VDS > 0, the MOSFET is always on. Note: V + = VOUT = VDS . We know that for 0 < V + < 10 V, the MOSFET is on. So there are two possible regions of operation in that voltage range: LINEAR or SATURATION. Find the VDS required for SATURATION: VDS (sat) = VGS − VT H = 0 V − (−2 V) = 2 V. For 2 V < V + < 10 V, the transistor is in SATURATION, and the current value remains constant with a value: kn (VGS − VT h )2 2 ID = (1 mA/V2 )/2(0 V − (−2 V))2 ID = 0.002 A = 2 mA ID =

For 0 < V + < 2 V, the transistor is in LINEAR, and the current value depends on V + = VDS value:   2 VDS ID = kn (VGS − VT h )VDS − 2   V +2 2 + ID = 1 mA/V (0 − (−2))V − 2 +2 V mA ID = 2V + − 2 The plot is shown below, where ID and V + are in units of mA and V, respectively. Note that the plot only ends at V + = 3 V, but the current stays the same at 2 mA for voltages higher than 3 V....