ECE216 Question Bank PDF

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ECE216-DIGITAL ELECTRONICS LABORATORYQUESTION BANKSECTION-1 QUESTIONS BASED ON LABORATORY AND SOFTWARE.Q.1 is the IC No for NOT gate(A) 7404 (B) 7408 (C) 7432 (D) 7400Q.2 is the IC No for NOR gate(A) 7404 (B) 7400 (C) 7402 (D) 7432Q.3 is the IC No for NAND gate(A) 7404 (B) 7400 (C) 7402 (D) 7432Q.4 ...

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ECE216-DIGITAL ELECTRONICS LABORATORY QUESTION BANK SECTION-1 QUESTIONS BASED ON LABORATORY AND SOFTWARE. Q.1.What is the IC No for NOT gate (A) 7404

(B) 7408

(C) 7432

(D) 7400

Q.2.What is the IC No for NOR gate (A) 7404

(B) 7400

(D) 7432

(C) 7402

Q.3.What is the IC No for NAND gate (A) 7404

(C) 7402

(B) 7400

(D) 7432

Q.4.What is the IC No for EX-OR gate (A) 7486

(B) 7432

(C) 7488

(D) 6532

Q.5.In IC7408 pin no 7 and 14 Represent is (A) GND,VCC (B) GND,GND (C)VCC,VCC (D) VCC,GND Q-6.How many 2 input AND gate are included in IC7408 (A) 4 (B) 3 (C) 2 (D) 5 Q-7. What is the IC No for AND gate (A) 7410 (B) 7408

(C) 7400

(D) 7432

Q-8. What is the IC No for OR gate (A) 7435 (B) 7432 (C) 7460 (D) 7400 Q-9.How many 2 input OR gate are included in IC7432 (A) 4 (B) 3 (C) 2 (D) 5 Q-10. How many NOT gate are included in Hex Inverter (A) 5 (B) 4 (C) 6 (D) 9 Q.11.How many 2 input NOR gate are included in IC7402

(A) 4 (B) 3 (C) 2 (D) 5 Q.12.How many 2 input NAND gate are included in IC7400 (A) 4 (B) 3 (C) 2 (D) 5 Q.13.How many 2 input XOR gate are included in IC7486 (A) 4 (B) 3 (C) 2 (D) 5 Q.14.In Full adder how many XOR and AND gates are used (A) 2,3 (B) 3,3 (C) 2,2 (D) 2,1 Q.15.In Full adder Sum is given last which gate (A) AND (B) OR (C) NAND (D) XOR Q.16.In Full adder Carry is given last which gate (A) AND (B) OR (C) NAND (D) XOR Q.17.In Half Subtractor how many total gates are used including outputs if NOT gate is also used (A) 5 (B) 10 (C) 7 (D) 4 Q.18.In proteus what is the device code for 4:1 MUX (A) 74LS153 (B) 74LS6567 (C) 756783LS (D) 74LS154 Q.19.In proteus what is the device code for 3:8 Decoder (A) 74LS142 (B) 74LS138 (C) 756783LS (D) 74LS154 Q.20.In 74LS138 Pin No 15,14,13,12,11,10,9 and 7 are (A) Input Pins (B) Output Pins (C) Ground (D) VCC Q.21.In 74LS138 Pin No 1,2 and 3 are (A) Input Pins (B) Output Pins (C) Ground (D) VCC Q.22.IC No for Triple 3 input NAND gate are (A) 7410 (B) 7400 (C) 7409 (D) 7411

Q.23.IC No for JK Flip Flop are (A) 4029 (B) 4028 (C) 4027 (D) 4020 Q.24.How many types of Sequential circuits are used: (A) 2 (B) 3 (C) 4 (D) 5 Q.25. In _______ circuits, the state of the device changes only at discrete times in response to a clock Pulse. (A) Discrete (B) Asynchronous (C) Combinational (D) Synchronous Q.26. In _______ circuits, is not synchronized by a clock signal; the outputs of circuit change directly in response to change in inputs. (A) Discrete (B) Asynchronous (C) Combinational (D) Synchronous Q.27. What is condition of toggle condition in JK Flip Flop (for positive edge triggered)? (A) J=1, K=0, and clk=1 (B) J=0, K=1, and clk=1 (C) J=1, K=1, and clk=0 (D) J=1, K=1, and clk=1 Q.28. What is the condition of the next state of counter if present state is Q0=0, Q1=0, Q2=0(up counter)? (A) Q0=0, Q1=0, Q2=1 (B) Q0=1, Q1=0, Q2=0 (C) Q0=0=1, Q1=1, Q2=0 (D) Q0=1, Q1=1, Q2=1 Q.29.What is Pin No 3,4,9 and 11 in IC 4027?

(A) ClK2,Reset 2,Set 1 and K1 (B) ClK1,Reset 1,Set 1 and K1 (C) ClK2,Reset 2,Set 2 and J1 (D) ClK2,Reset 2,Set 2 and K1 Q.30.The IC No for 4 Bit Ripple Counter or MOD10 Counter is (A) 7498 (B) 7496 (C) 7493 (D) 7400 Q.31.The IC No for BCD to 7 Segment display converter is (A) 7498 (B) 7488 (C) 7493 (D) 7448 Q.32.7 Segment display is of which type (A) Common Cathode (B) Common Anode (C) Common (D) Sequential Q.33. The IC No for Dual D flip flop(Preset Clear are active high) is (A) 4044 (B) 5013 (C) 7493 (D) 4013 Q.34.In proteus what is the device code for Dual D flip flop(Preset Clear are active low) (A) 74LS142 (B) 74LS74 (C) 756783LS (D) 74LS154 Q.35. Some Functions of register are (A) retrive data from register (B) store/load new data into register (C) Shift the data within register (D) All of the Above

Q.36. The shift register used for the storage or transfer of binary data are: (A) SISO and SIPO (B) PISO AND PIPO (C) Both a and b (D) None of the above Q.37. SIPO will provide number of outputs equal to _______ (A) Flip flops (B) Number of inputs (C) Both a and b (D) None of the above SECTION-2 THEORY QUESTIONS: Q.38. How many truth table entries are necessary for a four-input circuit? (A) 4 (B) 16 (C) 10 (D) 12 Q.39.Which input values will cause an AND logic gate to produce a HIGH output? (A) At least one input is HIGH (B) At least one input is LOW (C) All inputs are HIGH (D) All inputs are LOW Q.40.Exclusive-OR (XOR) logic gates can be constructed from what other logic gates? (A) OR gates only (B) AND gates and NOT gates (C) AND gates, OR gates, and NOT gates (D) OR gates and NOT gates

Q.41. The AND function can be used to ___________ and the OR function can be used to _____________ (A) enable, disable (B) disable, enable (C) Synchronize, energize (D) Detect, invert Q.42.Complement of the expression A’B + CD’ is _________ (A) (A’ + B)(C’ + D) (B) (A + B’)(C’ + D) (C) (A’ + B)(C’ + D’) (D) (A’ + B’)(C + D’) Q.43. Simplify Y = AB’ + (A’ + B)C. (A) AB’ + C (B) A’B + AC (C) A’B + AC’ (D) A’B + A’ Q.44. The boolean function A + BC is a reduced form of ____________ (A) ABC + BC (B) (A + B)(A + C) (C) A’B + AB’C (D) (A + C)B Q.45. In parts of the processor, adders are used to calculate ____________ (A) Addresses (B) Table indices (C) Increment and decrement operators (D) All of the Mentioned Q.46. In which operation carry is obtained? (A) Subtraction

(B) Addition (C) Multiplication (D) Both addition and subtraction Q.47. If A and B are the inputs of a half adder, the sum is given by __________ (A) A AND B (B) A OR B (C) A XOR B (D) A EX-NOR B Q.48. If A and B are the inputs of a half adder, the carry is given by __________ (A) A AND B (B) A OR B (C) A XOR B (D) A EX-NOR B Q.49.The difference between half adder and full adder is __________ (A) Half adder has two inputs while full adder has four inputs (B) Half adder has one output while full adder has two outputs (C) Half adder has two inputs while full adder has three inputs (D) All of the Mentioned Q.50.A, B and C are the inputs of a full adder then the sum is given by __________ (A) A AND B AND C (B) A OR B AND C (C) A XOR B XOR C (D) A OR B OR C Q.51. If A, B and C are the inputs of a full adder then the carry is given by __________ (A) A AND B OR (A OR B) AND C

(B) A OR B OR (A AND B) C (C) (A AND B) OR (A AND B)C (D) A XOR B XOR (A XOR B) AND C Q.52. Half subtractor is used to perform subtraction of ___________ (A) 3 bits (B) 4 bits (C) 2 bits (D) 5 bits Q.53. Let A and B is the input of a subtractor then the output will be ___________ (A) A XOR B (B) A AND B (C) A OR B (D) A EXNOR B Q.54. Let A and B is the input of a subtractor then the borrow will be ___________ (A) A AND B’ (B) A’ AND B (C) A OR B (D) A AND B Q.55.The full subtractor can be implemented using ___________ (A) Two XOR and an OR gates (B) Two half subtractors and an OR gate (C) Two multiplexers and an AND gate (D) Two comparators and an AND gate Q.56. The output of a subtractor is given by (if A, B and X are the inputs). (A) A AND B XOR X (B) A XOR B XOR X

(C) A OR B NOR X (D) A NOR B XOR X Q.57. The output of a full subtractor is same as ____________ (A) Full adder (B) Half adder (C) Half subtractor (D) Decoder Q.58. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct

(A) d (B) a (C) c (D) b Q.59. Which of the following combinations of logic gates can decode binary 1101? (A) One 4-input AND gate (B) One 4-input AND gate, one inverter (C) One 4-input AND gate, one OR gate (D) One 4-input NAND gate, one inverter

Q.60. What is a multiplexer? (A) It is a type of decoder which decodes several inputs and gives one output (B) A multiplexer is a device which converts many signals into one (C) It takes one input and results into many output (D) It is a type of encoder which decodes several inputs and gives one output Q.61. If the number of n selected input lines is equal to 2 m then it requires _____ select lines. (A) 2 (B) m (C) n (D) 2n Q.62. How many NOT gates are required for the construction of a 4-to1 multiplexer? (A) 3 (B) 4 (C) 2 (D) 5 Q.63. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is

(A) X0 (B) X1 (C) X2 (D) X3 Q.64. The enable input is also known as ___________ (A) Select input (B) Decoded input (C) Strobe (D) Sink

Q.65. Why is a demultiplexer called a data distributor? (A) The input will be distributed to one of the outputs (B) One of the inputs will be selected for the output (C) The output will be distributed to one of the inputs (D) Single input to Single Output Q.66.In 1-to-4 demultiplexer, how many select lines are required? (A) 2 (B) 3 (C) 4 (D) 5 Q.67. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________

(A) Y0 (B) Y1 (C) Y2 (D) Y3 Q.68. The truth table for an S-R flip-flop has how many VALID entries? (A) 1 (B) 2 (C) 3 (D) 4 Q.69. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called ________________ (A) Combinational circuits (B) Sequential circuits (C) Latches (D) Flip-flops

Q.70.Whose operations are more faster among the following? (A) Combinational circuits (B) Sequential circuits (C) Latches (D) Flip-flops Q.71. The basic latch consists of ___________ (A) Two inverters (B) Two comparators (C) Two amplifiers (D) Two adders Q.72. The output of latches will remain in set/reset until ___________ (A) The trigger pulse is given to change the state (B) Any pulse given to go into previous state (C) They don’t get any pulse more (D) The pulse is edge-triggered Q.73.What is a trigger pulse? (A) A pulse that starts a cycle of operation (B) A pulse that reverses the cycle of operation (C) A pulse that prevents a cycle of operation (D) A pulse that enhances a cycle of operation Q.74. The characteristic equation of S-R latch is ____________ (A) Q(n+1) = (S + Q(n))R’ (B) Q(n+1) = SR + Q(n)R (C) Q(n+1) = S’R + Q(n)R (D) Q(n+1) = S’R + Q'(n)R Q.75. What is one disadvantage of an S-R flip-flop? (A) It has no Enable input (B) It has a RACE condition

(C) It has no clock input (D) Invalid State Q.76.On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________ (A) The clock pulse is LOW (B) The clock pulse is HIGH (C) The clock pulse transitions from LOW to HIGH (D) The clock pulse transitions from HIGH to LOW Q.77. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________ (A) Two AND gates (B) Two NAND gates (C) Two NOT gates (D) Two OR gates Q.78. How many flip-flops are in the 7475 IC? (A) 2 (B) 1 (C) 4 (D) 8 Q.79. Which of the following is correct for a gated D flip-flop? (A) The output toggles if one of the inputs is held HIGH (B) Only one of the inputs can be HIGH at a time (C) The output complement follows the input when enabled (D) Q output follows the input D when the enable is HIGH Q.80.The characteristic equation of D-flip-flop implies that ___________ (A) The next state is dependent on previous state (B) The next state is dependent on present state (C) The next state is independent of previous state (D) The next state is independent of present state Q.81. The S-R latch composed of NAND gates is called an active low circuit because _____________

(A) It is only activated by a positive level trigger (B) It is only activated by a negative level trigger (C) It is only activated by either a positive or negative level trigger (D) It is only activated by sinusoidal trigger Q.82. The characteristic equation of J-K flip-flop is ______________ (A) Q(n+1)=JQ(n)+K’Q(n) (B) Q(n+1)=J’Q(n)+KQ'(n) (C) Q(n+1)=JQ'(n)+KQ(n) (D) Q(n+1)=JQ'(n)+K’Q(n) Q.83. Master slave flip flop is also referred to as? (A) Level triggered flip flop (B) Pulse triggered flip flop (C) Edge triggered flip flop (D) Edge-Level triggered flip flop Q.84.For D flip-flop to JK flip-flop, the characteristics equation is given by ___________ (A) D=JQ(p)’+Q(p)K’ (B) D=JQ(p)’+KQ(p)’ (C) D=JQ(p)+Q(p)K’ (D) D=J’Q(p)+Q(p)K Q.85. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops? (A) 0 to 2n (B) 0 to 2n + 1 (C) 0 to 2n – 1 (D) 0 to 2n+1/2 Q.86. Ripple counters are also called ____________ (A) SSI counters (B) Asynchronous counters

(C) Synchronous counters (D) VLSI counters Q.87. How many natural states will there be in a 4-bit ripple counter? (A) 4 (B) 8 (C) 16 (D) 32 Q.88. The terminal count of a typical modulus-10 binary counter is ____________ (A) 0000 (B) 1010 (C) 1001 (D) 1111 Q.89. A down counter using n-flip-flops count ______________ (A) Downward from a maximum count (B) Upward from a minimum count (C) Downward from a minimum to maximum count (D) Toggles between Up and Down count Q.90. UP-DOWN counter is a combination of ____________ (A) Latches (B) Flip-flops (C) UP counter (D) Up counter & down counter Q.91. In an UP-counter, each flip-flop is triggered by ___________ (A) The output of the next flip-flop (B) The normal output of the preceding flip-flop (C) The clock pulse of the previous flip-flop (D) The inverted output of the preceding flip-flop Q.92. A modulus-10 counter must have ________ (A) 10 flip-flops (B) 4 Flip-flops (C) 2 flip-flops (D) Synchronous clocking

Q.93. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________. (A) 0000 (B) 1111 (C)0111 (D)1000 Q.94. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time? (A) parallel-in, parallel-out (B) parallel-in, serial-out (C) serial-in, parallel-out (D) serial-in, serial-out Q.95. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

(A) 1101000000 (B) 0011010000 (C) 1100000000 (D) 0000000000 Q.96. What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time? (A) SIPO (B) PIPO (C) SISO (D) PISO Q.97. Which type of shift register is renowned as 'bit bucket brigade circuit' by presenting the input data and applying the clock pulse for

the movement of bits across the storage elements? (A) Serial In - Serial Out (SISO) (B) Serial In - Parallel Out (SIPO) (C) Parallel In - Parallel Out (PIPO) (D) Parallel In - Serial Out (PISO) Q.98. Match the following sequential Circuits with associated functions 1. Counter -------- A. Storage of Program & data in a digital computer 2. Register -------- B. Generation of timing variables to sequence the digital system operations 3. Memory --------- C. Design of Sequential Circuits (A) 1-A , 2-B , 3-C (B) 1-C , 2-B , 3-A (C) 1-C , 2-A , 3-B (D) 1-B , 2-C , 3-A Q.99. The full form of SIPO is ___________ (A) Serial-in Parallel-out (B) Parallel-in Serial-out (C) Serial-in Serial-out (D) Serial-In Peripheral-Out Q.100. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first) (A) 1100 (B) 0011 (C) 0000 (D) 1111

Note: 1.This are some important Questions given in this question bank. 2.Truth Table, Diagrams given in other edition of notes....