EMT 1250 L4 - Lab report PDF

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Freedom Titan EMT 1250L-E335 DIGITAL SYSTEMS LAB Experiment #4 Odd Parity Generator Professor C. Davidman

Date Performed: Monday October 1st, 2018 Date Due: Monday October 15th, 2018 Grade: Comments:

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Table of Contents Table of Contents…………..Page 2 Objective…………………..Page 3 Equipment………………….Page 3 Procedure……………………...Page 4 Logic Gates…………………….Page 5 Boolean Equations…………….Page 5 Truth Table…………………….Page 6 Logic Gate Circuit Diagram…...Page 6 Wiring Diagram……………….Page 7 Conclusion…………………….Page 8

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Objective To show how “AND” and “OR” Gates could be used to generate an ODD Bit.

IC Chip pin-outs

Equipment: Digital Trainer AND Gate (7408) OR Gate (7432)

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Procedure: 1. When digital information is transmitted from one device to another, a check is made to determine if the received data is good or bad. One such error checking scheme is called PARITY check and it will detect errors (but not all). 2. With each 3 bits of data that the sender sends the odd parity generator sends a PARITY that the total number of “1”s that is sent is an ODD number (1 or 3). The receiver checks the total number of “1”s that is received. If it is an odd number then he has confidence that the data is correct, an even number of 1’s means there is an error. 3. The odd parity generator logic diagram is shown in the figure below. Use the switches A, B, C to provide the inputs to the gates and connect the output of the OR (labeled odd parity to an LED.) 4. Record your test results of the ODD PARITY GENERATOR logic circuit to obtain: a-the truth table; b-a clear statement of output as a function of inputs; c-the Boolean equation. 5. Describe in your own words, how an odd parity generator is used to send and check good data.

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Logic Gates: AND Gate:-

OR Gate:-

Logic/Boolean Expression(s): Y = A'B'C' + A'BC + AB'C + ABC'

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Truth Table: INPUT

OUTPUT

A

B

C

Y

0

0

0

1

0

0

1

0

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

0

Logic Gate Circuit Diagram:

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Wiring Diagram:

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Conclusion: With odd parity, the total number of 1's in the data plus parity bit must be an odd number. The sender sends an odd bits of data and it the receiver receives odd bits, then the dates is good. But if there receiver received even bits of data then the data is bad. Thus, if there are already an odd number of 1's in the data itself the parity bit generated is 0, but if there are an even number of 1's in the data itself, the parity bit generated is 1 to make the total odd. If a single bit is switched during transmission, a parity check will catch it, and we know the data are bad. We can't tell, however, which bit was switched.

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