Experiment NO-1 LAB PDF

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Summary

Experiment NO-1 LAB MPMC LAB...

Description

EXPERIMENT NO-1 Familiarization with 8085 Microprocessor procedures, 8085 Instruction sets and programs.

Kit,

self-testing

PART-I (Familiarization with 8085 Microprocessor Kit) The 8085 microprocessor Kit i.e. SDA-85 is a compact, versatile, low-cost microprocessor trainer consisting of the 8085 CPU, provision for 64K memory (ROM and RAM), Timer, Parallel I/O, Serial I/O, 28 keys keyboard, 6 digit display, optional EPROM programmer Interface and provision for battery back-up for RAM. A powerful monitor program of 16K bytes of EPROM allows program entry, verification, execution and debugging, line assembly and disassembly, transfer of files to and from a PC EPROM programmer interface routine etc. In Table 1, the important ICs used in 8085 mp kit are described. In Table 2, the memory addressing decoding scheme and in Table 3 self-testing procedure is described. Figs. 1(a), 1(b) & 1(c) show the layout diagram of 8085 microprocessor kit, pin configuration & architecture of 8085 microprocessor kit respectively.

Fig. 1(a): Layout diagram of 8085 Microprocessor Kit

Table 1: Important ICs used in 8085 MP KIT

Label No. U1 U3

IC (Pin) 6223,992825 (16) 8255 (40)

Used as MAX 232C Programmable Peripheral Interface

U4 U5

8255 40) 8279 (40)

Programmable Peripheral Interface Keyboard Display Controller

U6

8251 (28)

U8

74LS14 (14)

Universal Synchronous Asynchronous Receiver Transmitter (USART) Hex Inverter

U9 U10

74156 (16) 74240 (20)

Octal 1:4 Demultiplexer Octal Buffer

U11

8253 (24)

Programmable Interval Timer (PIT)

U12 U13

8259 (28) 7407 (14)

Programmable Interrupt Controller (PIC) Hex Buffer

U22 U23 U24 U25

6264/62256 (28) 4053 (16) 7400 (14) 16L8 (20)

U26 U27

7474 (14) 27128 (28)

Dual D-Flip Flop EPROM (16KB)

U28 U29 U30 U31

74240 (20) 27128 (28) 74373 (20) 8085 (40)

Octal Buffer Monitor Program (16KB) (EPROM) Latch/ Flip Flop 8-bit Microprocessor

RAM (8K) /RAM (32KB) Triple 2:1 MUX NAND Gate Programmable Logic Device (PLD)

Fig. 1(b): Pin diagram of 8085 microprocessor

Table 2: Memory Address Decoding for 8085 MP

27128 (U29)

27128 (U27)

62256/6264 (U22)

0000H-3FFFH

4000H-7FFFH

(Monitor Program)

(EPROM Expansion)

8000H-FFFFH / E000H-FFFFH (RAM Space)

Table 3: Self testing Procedures Test Program

Address

Description

Display Test Syntax: Go 2190H

Keyboard Test Syntax: Go 2180H

2190H

Each segment is switched on sequentially.

2180H

On pressing any key the scan cods of the key will be displayed.

RAM Test Syntax: Go 2150H starting addrending addr

2150H

Sign on displayed.

8255 Test Syntax: Go 21E0H

21E0H

If with 8255s are good, the message 8255 will be displayed. (Short P2 and P3 using 26 pin flat cable).

message

will

be

Fig. 1(c): Architecture of 8085 microprocessor

PART-II

8085 Instruction Set (Data Transfer Group, Arithmetic Group) The students will be demonstrated about the 8085 Data Transfer Group and Arithmetic Group of Instructions. An instruction is a command given to the computer to perform a specified operation that the microprocessor is designed to execute. The instruction set consists of one byte, two byte and three byte instructions. The first byte is always the opcode. In two byte instructions, the first byte is opcode and the second byte is usually data. In three byte instructions, the last 2 bytes represent some address. In Table 1 & 2, the data transfer group and arithmetic instructions have been explained. Then three verification programs have been demonstrated to the students which signifies the use of MVI r,data, INR r and DCR r instructions.

Table 1: Data Transfer Group Sl. No.

Instruction

Operation Performed

1) 2)

MVI r,data MVI M,data

3) 4)

MOV r1,r2 MOV M,r

5)

MOV r,M

6) 7) 8) 9) 10) 11)

LXI rp,data STA addr LDA addr SHLD addr LHLD addr LDAX rp

12)

STAX rp

13)

XCHG

Move data immediate to register r. Move data immediate to memory whose address is in H & L pair. Move data from one register (r2) to another register (r1). Move data from register r to memory whose address is in H & L pair. Move data from memory location specified by H & L pair to register r. Load immediate register pairs with double byte data. Store data from A direct at the address that follows Load data into A direct from the address that follows Store H & L direct Load H & L direct Load A with the contents of the memory location whose address is in rp, B-C, D-E Store contents of A in memory whose address is in register pair B-C, D-E Exchange contents of register H with D and L with E

Table 2: Arithmetic Group 1.

Increment & Decrement

Sl. Instruction No. i) INR r ii) INR M iii) INX rp iv) DCR r v) DCR M vi) DCX rp 2.

Operation Performed Increment register Increment data in memory Increment register pair Decrement register Decrement data in memory Decrement register pair

Add

Sl. Instruction No. i) ADD r ii) ADD M iii) ADI data iv) ADC r v) ADC M vi) ACI data vii) DAD rp

Operation Performed Add register r to A Add data in memory to A Add data immediate to A Add register r with carry to A Add data in memory to A with carry Add immediate data to A with carry Add register pair rp to H & L pair

Verification of the instruction INR r : Check the contents of B after execution of the following instructions. MVI B,08H ; Move 08H to register B INR B ; Increment the contents of register B HLT ; Restart Address

Hex Code

Mnemonics

Comments

0080H

06,08

MVI B,08H

Move 08H to register B

0082H

04

INR B

Increment the contents of register B

0083H

CF

RST 1

Halt

OBSERVATION :-Result: Reg. B = 09H...