Field-Effect Transistors (FETs) and Circuits PDF

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Lecture 15: Field-Effect Transistors (FETs) Lecture 16: DC Biasing Circuits of JFETs Lecture 17: JFET Small-Signal Analysis
Lecture 18: Frequency Response of JFET Amplifiers...

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Part III Lectures 15-18 Field-Effect Transistors (FETs) and Circuits

Field-Effect Transistors (FETs) Lecture Fifteen - Page 1 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

Field-Effect Transistors (FETs) Basic Definitions: The FET is a semiconductor device whose operation consists of controlling the flow of current through a semiconductor channel by application of an electric field (voltage). There are two categories of FETs: the junction field-effect transistor (JFET) and the metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET category is further broken-down into: depletion and enhancement types.

A Comparison between FET and BJT: ⯇ FET is a unipolar device. It operates as a voltage-controlled device with either electron current in an n-channel FET or hole current in a p-channel FET. ⯇ BJT made as npn or as pnp is a current-controlled device in which both electron current and hole current are involved. ⯇ The FET is smaller than a BJT and is thus for more popular in integrated circuits (ICs). ⯇ FETs exhibit much higher input impedance than BJTs. ⯇ FETs are more temperature stable than BJTs. ⯇ BJTs have large voltage gain than FETs when operated as an amplifier. ⯇ The BJT has a much higher sensitivity to changes in the applied signal (faster response) than a FET.

Junction Field-Effect Transistor (JFET): The basic construction of n-channel (p-channel) JFET is shown in Fig. 15-1a (b). Note that the major part of the structure is n-type (p-type) material that forms the channel between the embedded layers of p-type (n-type) material. The top of the n-type (p-type) channel is connected through an ohmic contact to a terminal referred to as the drain "D", while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source "S". The two p-type materials are connected together and to the gate "G" terminal.

p

n-channel

Gate (G)

D p

G

G

n

p-channel

D

Drain (D)

D n

S

G S

Source (S)

S

(a) Fig. 15-1

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

(b)

Fig. 15-1

Field-Effect Transistors (FETs) Lecture Fifteen - Page 2 of 8 Dr. Ahmed Saadoon Ezzulddin

Field-Effect Transistors (FETs) Lecture Fifteen - Page 3 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

Basic Operation of JFET: ⯇ Bias voltages are shown, in Fig. 15-2, applied to an n-channel JFET devise. ⯇ VDD provides a drain-to-source voltage, VDS, (drain is positive relative to source) and supplies current from drain to source, ID, (electrons move from source to drain). ⯇ VGG sets the reverse-bias voltage between the gate and the source, VGS, (gate is biased negative relative to the source). ⯇ Input impedance at the gate is very high, thus the gate current IG = 0 A. ⯇ Reverse biasing of the gate-source junction produces a depletion region in the n-channel and thus increases its resistance. ⯇ The channel width can be controlled by varying the gate voltage, and thereby, ID can also be controlled. ⯇ The depletion regions are wider toward the drain end of the channel because the reverse-bias voltage between the gate and the drain is grater than that between the gate and the source. ID Depletion regions D



IG  0 A G

p

p

VDS 

VDD



VGS VGG 

n

Electron flow S

Fig. 15-2

JFET Characteristics: ⯇ When VGS = 0 V and VDS < VP

(pinch-off voltage)*: ID rises linearly with VDS

(ohmic region, n-channel resistance is constant), as shown in Fig. 15-3.

 When VDS is increased to a level where it appears that the two depletion regions would "touch", a condition referred to as pinch-off will result. The level of V DS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP.

Field-Effect Transistors (FETs) Lecture Fifteen - Page 3 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

D n G +  0V VGS _

+

p

I D (mA)

I

p

DSS

Increasing resistance due to narrowing channel

VDSP V n.channel resistance

ID

_

S

Fi

0

VDS (V )

VP

g. 15-3 ⯇ When VGS = 0 V and V  D as shown in Fig. 15- S VP 4.

: ID remains at its saturation value IDSS beyond VP,

I D (mA)

D

I

n G +  0V VGS _

p

+ p

I DSS S

V V DS

Saturation level DSS

VGS  0V

P

_

VDS (V ) 0

VP

Fig. 15-4 ⯇ When VGS < 0 and VDS some positive value: The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with VGS = 0 V but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at lower level of VDS, as shown in Fig. 15-5.

Field-Effect Transistors (FETs) Lecture Fifteen - Page 4 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

Summary: For n-channel JFET:  VP 1. The maximum current is defined as IDSS and occurs when VGS = 0 V and VDS as shown in Fig. 15-6a. 2. For gate-to-source voltages VGS less than (more negative than) the pinch-off level, the drain current is 0 A (ID = 0 A) as appearing in Fig. 15-6b. 3. For all levels of VGS between 0 V and the pinch-off level, the current ID will range between IDSS and 0 A, respectively, as shown in Fig. 15-6c.

(a)

(b)

(c) Fig. 15-6 For p-channel JFET a similar list can be developed (see Fig. 15-7).

Field-Effect Transistors (FETs) Lecture Fifteen - Page 5 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

Shockley's Equation: For the BJT the output current IC and input controlling current IB were related by β, which was considered constant for the analysis to be performed. In equation form: control variable

↓ IC    ↑ constant

In the above equation a linear relationship exists between IC and IB. Unfortunately, this linear relationship does not exist between the output (ID) and input (VGS) quantities of a JFET. The relationship between ID and VGS is defined by Shockley's equation: control variable

↓ V 2 I D  I DSS 1 V  PGS 

[15.1] constant

↑

↑

The squared term of the equation will result in a nonlinear relationship between ID and VGS, producing a curve that grows exponentially with decreasing magnitude of VGS.

Transfer Characteristics: Transfer characteristics are plots of ID versus VGS for a fixed value of VDS. The transfer curve can be obtained from the output characteristics as shown in Fig. 15-8, or it can be sketched to a satisfactory level of accuracy (see Fig. 15-9) simply using Shockley's equation with the four plot points defined in Table 15-1.

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

Fig. 15-8

Field-Effect Transistors (FETs) Lecture Fifteen - Page 6 of 8 Dr. Ahmed Saadoon Ezzulddin

Field-Effect Transistors (FETs) Lecture Fifteen - Page 7 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

I D (mA)

Table 15-1

IDSS

 V 2 I D  I DSS 1  GS  VP   VGS (V) ID (mA) IDSS 0 0.3 VP IDSS / 2 0.5 VP IDSS / 4 VP 0

IDSS / 2 IDSS / 4 VP 0.5V

V GS (V )

0 0.3

V P

P

Fig. 15-9

Important Relationships: A number of important equations and operating characteristics have introduced in the last few sections that are of particular importance for the analysis to follow for the dc and ac configurations. In an effort to isolate and emphasize their importance, they are repeated below next to a corresponding equation for the BJT. The JFET equations are defined for the configuration of Fig. 15-10a, while the BJT equations relate to Fig. 15-10b.

(a)

(b) Fig. 15-10

JFET  V 2 I D  I DSS 1  GS  

VP 

BJT  IC I D

 IB  IS

Field-Effect Transistors (FETs) Lecture Fifteen - Page 8 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010



 IE

IC IG  0 A

 VBE

 0.7V

Transconductance Factor: The change in drain current that will result from a change in gate-to-source voltage can be determined using the transconductance factor gm in the following manner: ID  gm  The transconductance factor, gm, (on specification sheets, gm is provided as yfs) is the slop of the characteristics at the point of operation, as shown in Fig. 15-11. That is,  ID g m y fs V GS VDS const. Fig. 15-11 An equation for gm can be derived as follows:  V 2  dI d  D gm   I DSS 1  GS    I

d  V 2 1  GS 

DSS

dVGS  VP  dVGS Q pt. dVGS     VGS  d  VGS   VGS   dV 1  V gm  2I DSS 1    2I DSS 1  V

V

VP  1

0  V 





GS



P



 2I DSS VGS  1  V  V P P 

gm and g mo where gm

P

 2I DSS VP is the value of gm at VGS = 0 V.



P



P



[15.2]

[15.3]

o

Equation [15.2] then becomes:  V gmm g o 1   GS  VP 

[15.4]

JFET Output Impedance: The output impedance (rd) is defined on the drain (output) characteristics of Fig. 15-12 as the slope of the horizontal characteristic curve at the point of operation. In equation form: 1  VDS rd  [15.5] y I D VGS const. os

where yos is the output admittance, with the units of μS, as appear on JFET specification sheets.

Fig. 15-12

JFET AC Equivalent Circuit: The control of Id by Vgs is include as a current source gmVgs connected from drain to source as shown in Fig. 15-13. The current source has its arrow pointing from drain to source to establish a 180o phase shift between output and input voltages as will as occur in actual operation. The input impedance is represented by the open circuit at the input terminals and the output impedance by the resistor rd from drain to source. Id g

d

+



gmVgs

Vgs s

_

rd

Vds 

s

Fig. 15-13

Exercises: 1. Sketch the transfer curve defined by IDSS = 12 mA and VP = − 6 V. 2. For a JFET with IDSS = 8 mA and VP = − 4 V, determine: a. the maximum value of gm (that is, gm o ), and b. the value of gm at the following dc bias points: VGS = − 0.5 V, VGS = − 1.5 V, and VGS = − 2.5 V. 3. Given yfs = 3.8 mS and yos = 20 μS, sketch the JFET ac equivalent model.

DC Biasing Circuits of JETs Lecture Sixteen - Page 1 of 8 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

DC Biasing Circuits of JFETs 1. Fixed-Bias Configuration: For the circuit of Fig. 16-1, I G  0 A ,  0V . and VR G  IG RG

For the input circuit,  VGG  VGS  0 , and VGS  VGG

 

VDS 

VGS 

Fig. 16-1

From Shockley's equation:  V 2 I D  IDSS 1  GS  VP  For the output circuit,  0 , VDD  I D RD  VDS and

VDS  VDD  I D RD

A graphical analysis is shown in Fig. 16-2.

Fig. 16-2

Example 16-1: For the circuit of Fig. 16-1 with the following parameters: IDSS = 10 mA, VP = − 8 V, VDD = + 16 V, VGG = 2 V, RG = 1 MΩ, and RD = 2 kΩ, determine the following: VGSQ, IDQ, VDS, VD, VG, and VS. Solution: From Fig. 16-3: VGSQ  VGG  2V , and

I DQ  5.6mA.

VD  V  I R DD D D S  16  (5.6m)(2k )  4.8V .

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

VD   4.8V VDS VG  . VGS VS   2V . 0V .

DC Biasing Circuits of JETs Lecture Sixteen - Page 2 of 8 Dr. Ahmed Saadoon Ezzulddin

Fig. 16-3

2. Self-Bias Configuration: For the circuit of Fig. 16-4, IG  0 A, and VR G  IG  0V . RG I I , D

S

and V R

 I D RS . S

For the input circuit,  VGS  V RS  0 and VGS  I D RS,

Fig. 16-4

From Shockley's equation: 2  I D  IDSS 1  VGS  VP  For the output circuit, VDD  VR  VDS  V D

and

RS

Self-bias line

0,

VDS  VDD  I D (RD  RS )

A graphical analysis is shown in Fig. 16-5.

Fig. 16-5

Example 16-2:

For the circuit of Fig. 16-4 with the following parameters: IDSS = 8 mA, VP = − 6 V, VDD = + 20 V, RG = 1 MΩ, RS = 1kΩ, and RD = 3.3 kΩ, determine the following: VGSQ, IDQ, VDS, VG, VS, and VD. Solution:

I D  4mA , we obtain

Choosing VG  I D  (4m)(1k )  4V . S RS At the Q-point (see Fig. 16-6): VGSQ  2.6V , and IDQ  2.6mA .

VD  V  I (R  R ) DD D D S S  20  (2.6m)(1k  3.3k )  8.82V . VG  0V , and

VS  I D  (2.6m)(1k )  2.6V . RS VD  VDD  I D RD  20  (2.6m)(3.3k )  11.42V ,  V  8.82  2.6  11.42V . or VD  S VDS

Fig. 16-6

Example 16-3 (Common-Gate Configuration): For the common-gate configuration of Fig. 16-7, determine the following: VGSQ, IDQ, VD, VG, VS, and VDS.

C2

C1

Fig. 16-7 Solution:

I D  6mA , we obtain Choosing VGS

 I D RS

 (6m)(680)  4.08V .

At the Q-point (see Fig. 16-8): VGSQ  2.6V , and I DQ  3.8mA . VD  VDD  ID RD  12  (3.8m)(1.5k )  6.3V . VG  0V .  (3.8m)(680)  2.58V . VS  I D RS VD  VD  S VS

 6.3  2.58  3.72V .

Example 16-4 (Design): For the circuit of Fig. 16-9, the levels of VDQ and IDQ are specified. Determine the required values of RD and RS.

Fig. 16-9 Solution: RD  

VRD

20   VDD  VDQ 12 25m  3.2k . I DQ

I DQ

Plotting the transfer curve as shown in Fig. 16-10 and drawing a horizontal line at IDQ = 2.5 mA will result in VGSQ = − 1 V, and applying VG  I D will establish the level of RS : S RS  RGSQ V S

 I DQ



 (1)

 0.4k

. 2.5m Fig. 16-10

3. Voltage-Divider Bias Configuration: For the circuit of Fig. 16-11, I R  IR , IG  0 A 1 2   VDD  R2 and V G . R 12R For the input circuit, VRGS  VGS  V RS  0 , V  I S  I D RS and R VS  V  ,I R GS

G

D

S

From Shockley's equation:  V 2 I D  IDSS 1  GS  VP 

Voltage-divider bias line

For the output circuit, VDD  VR D  VDS  V R S  0 , VDS  VDD  I D (RD  RS )

and

A graphical analysis is shown in Fig. 16-12.

Fig. 16-12

Example 16-5:

For the circuit of Fig. 16-11 with the following parameters: IDSS = 8 mA, VP = − 4 V, VDD = + 16 V, R1 = 2.1 MΩ, R2 = 270 kΩ, RD = 2.4 kΩ, and RS = 1.5 kΩ, determine the following: VGSQ, IDQ, VD, VS, VDS, and VDG. Solution: V  G  VG S

VDD  R2

R1  R2   ID VG RS

(16)(270k  1.82V . ) 2.1M  270k  1.82  ID (1.5k ) ,

Fig. 16-13

when I D  0mA VG  1.82V , and S : 1.82 when  1.21mA . VG  0V I D  1.5k : S At the Q-point (see Fig. 16-13): VGSQ  1.8V , and IDQ  2.4mA .

VD  VDD  I D RD  16  (2.4m)(2.4k )  10.24V . VS  ID  (2.4m)(1.5k )  3.6V . RS VD  V  I (R  R )  16  (2.4m)(2.4k 1.5k )  6.64V , DD D D S S

or  VD   10.24  3.6  6.64V . VDS VS VDG  VD   10.24  1.82  8.42V . VG

Example 16-6 (Two Supplies): Determine the following for the circuit of Fig. 16-14; VGSQ, IDQ, VDS, VD, and VS.

Fig. 16-14

Solution: For the input circuit of Fig. 16-14, (KVL)  VGS  I S  VSS  RS 0 and IG  0 A ID  IS ,  VGS  VSS  I D RS VG  10  I (1.5k ) , D S

for I D  0mA VG  10V , and S ; 10 for  6.67mA. VG  0V I D 1.5k  ; S At the Q-point (see Fig. 16-15):

VGSQ  0.35V , and IDQ  6.9mA . For the output circuit of Fig. 16-14, VDD  I D RD  VDS  I S  VS  0 V  V  VRS  I S(R , R DS

DD

SS

D

D

S

VD  20  10  (6.9m)(1.8k  1.5k )  7.23V . S

VD  VDD  ID RD  20  (6.9m)(1.8k )  7.58V .  7.58  7.23  0.35V . VS  VD  VDS

Fig. 16-15

Example 16-7 (p-channel JFET): Determine VGSQ, IDQ, and VDS for the p-channel JFET of Fig. 16-16.

Fig. 16-16 Solution: V  R2

VDD  

(20)(20k )

 4.55V .

20k  68k R1  R2 VG   I  4.55  I D (1.8k) , D RS S VG when I D  0mA VG  4.55V , and S : G

 (4.55)  2.53mA . VG  0V I D  1.8k : S At the Q-point (see Fig. 16VGSQ  1.4V , I DQ  3.4mA. 17): and VD  VDD  I D (RD  RS )  20  (3.4m)(2.7k  1.8)  4.7V . when

S

Fig. 16-17

Exercises: 1. For the common-drain (source-follower) configuration of Fig. 16-18, determine the following: VGSQ, IDQ, VD, VG, VS, VDG, and VDS. VD D

C1

9 V IDSS

 16mA

VP  4V C2

Vi

RG 1M

Vo

RS 2.2k

Fig. 16-18

2. For the voltage-divider bias configuration of Fig. 16-19, if VD = 12 V and VGS = − 2 V, determine the value of RS.

Fig. 16-19

JFET Small-Signal Analysis Lecture Seventeen - Page 1 of 7 Dr. Ahmed Saadoon Ezzulddin

University of Technology Electrical and Electronic Engineering Department Second Year, Electronics I, 2009 - 2010

JFET Small-Signal Analysis Common-Source Configuration: The common-source configuration circuit of Fig. 17-1 includes a source resistor (RS) that may or may not be bypassed by a source capacitor (CS) in the ac domain. VDD



RD CC I o CG

Ii

D Zi

Rsig

 Vo

Zo

G





Vi



Vs





Z o RL

S RG

CS

RS

Fig. 17-1

Bypassed (abse...