4. NMOS and PMOS transistors operating principle PDF

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NMOS and PMOS transistors operating principle...

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Chapter 4

November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Transistors are active devices with highly nonlinear characteristics. Thus, to analyze and design a transistor circuit, we need models of transistors. Creating accurate models requires detailed knowledge of the physical operation of transistors and their parameters as well as a powerful analytical technique. A circuit can be analyzed easily using simple models, but there is generally a trade-off between accuracy and complexity. A simple model, however, is always useful to obtain the approximate values of circuit elements for use in a design exercise and the approximate performance of the elements for circuit evaluation. In this chapter, we will consider the operation and external characteristics of field-effect transistors using simple linear models. The basic concept of field-effect transistors (FETs) has been known since the 1930s; however, FETs did not find practical applications until the early 1960s. Since the late 1970s, MOSFETs have become very popular; they are being used increasingly in integrated circuits (ICs). The manufacturing of MOSFETs is relatively simple. A MOSFET device can be made small, and it occupies a small silicon area in an IC chip. MOSFETs are currently used for very-large-scale integrated (VLSI) circuits such as microprocessors and memory chips. A metal oxide semiconductor field-effect transistor (MOSFET) is a unipolar device. The current flow in a MOSFET depends on one type of majority carrier (electrons or holes). The output current of MOSFETs is controlled by an electric field that depends on a gate control voltage. There are two types of MOSFETs: enhancement MOSFETs and depletion MOSFETs.

There are two types of enhancement MOSFETs: -channel and -channel. An -channel enhancement MOSFET is often referred to as an NMOS. The physical structure of an NMOS showing its terminal is illustrated in Figure 4.1(a); a schematic appears in Figure 4.1(b). Since the -type substrate and the two  -type junctions are reverse biased, there will be a depletion region as shown in Figure 4.1(b) by shaded lines. Two  -type regions act as low-resistance connections to the source and the drain. An insulating layer of silicon dioxide is formed on top of the -type substrate by oxidizing the silicon. Ohmic contacts are provided to the  -regions for connection to the external circuit by leaving two windows on the silicon dioxide and depositing a layer of aluminum. The substrate B is normally connected to the source terminal. An -channel is induced under the influence of an electric field; there is no physical -channel between the drain and the source of an NMOS, as shown by the darker shade in Figure 4.1(b). The symbol for an NMOS is shown in Figure 4.1(c), where the arrow points from the -type region to the -type region. An NMOS is often represented by the abbreviated symbol shown in Figure 4.1(d) in which the arrowhead indicates the direction of the current.

AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Chapter 4

A -channel enhancement-type MOSFET, often referred to as a PMOS, is formed by two  -type regions on top of the -type substrate, as shown in Figure 4.2[(a) and (b)]. The -regions offer low resistances. The symbol for a PMOS is the same as that for an NMOS, except that the direction of the arrow is reversed, as shown in Figure 4.2(c). The abbreviated symbol is shown in Figure 4.2(d).

Figure 4.1 Structure and symbols of an -channel enhancement MOSFET

Figure 4.2 Structure and symbols of a -channel enhancement MOSFET

An NMOS is operated with positive gate and drain voltages relative to the source, as shown in Figure 4.3(a), whereas a PMOS is operated with negative gate and drain voltages relative to the source, as shown in Figure 4.3(b). Their substrates are connected to the source terminal. The NMOS can operate in any of the four operating regions: cutoff region, linear ohmic, nonlinear ohmic, and saturation.

Figure 4.3 Biasing of an NMOS and a PMOS AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Chapter 4

The complementary metal oxide semiconductor (CMOS) consists of an -channel enhancementmode device > 0 in series with a -channel enhancement-mode device  < 0. The crosssection of a CMOS is shown in Figure 4.4. The NMOS transistor is implemented directly in the type substrate, while the PMOS transistor is fabricated in a specially created region, known as an well. The two devices are isolated from each other by a thick region of oxide that functions as an insulator. An external body terminal is also made from the -type body and the -well. Due to their unique advantages, such as very low power consumption, CMOS circuits are commonly used in integrated circuits. The CMOS inverter, which is the basis of CMOS digital electronics, is covered in detail in section 4.3. CMOS technology has taken over many IC applications and continues to grow.

Figure 4.4 Cross section of a CMOS

The construction of an -channel depletion MOSFET is very similar to that of an NMOS. An actual channel is formed by adding -type impurity atoms to the -type substrate, as shown in Figure 4.5(a). The symbol for an -channel depletion MOSFET is shown in Figure 4.5(b); this symbol is often abbreviated to the one shown in Figure 4.5(c). Note that the vertical line is bold or darker. An -channel depletion MOSFET is normally operated with a positive voltage between the drain and the source terminals. However, the voltage between the gate and the source terminals can be positive, zero, or negative, whereas in an NMOS  is positive.

Figure 4.5 Schematic and symbols of an -channel depletion MOSFET AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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Chapter 4

November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

The operation of an -channel depletion MOSFET is similar to that of an NMOS. A depletion NMOS is off when its gate-to-source voltage   is less than− , whereas an NMOS is off when   ≤  . The channel is fully established at  = 0 for a depletion NMOS and at =  for an NMOS. Let us assume that the gate-to-source voltage is zero:  = 0. If  is increased from zero to some small value (≈ 1), the drain current follows Ohm’s law ( =  ⁄ ) and is directly proportional to  . Any increase in the value of  beyond  , known as the does not increase the drain current significantly. The region beyond pinch-down is called the The value of the drain current that occurs at   =   (with   = 0) is termed the drain-to-source saturation current  . Since the drain currents of the enhancement and depletion MOSFETs depend on the gate–source voltage, they are known as voltage-dependent devices and exhibit similar output characteristics and, the same model can be applied to both of them with reasonable accuracy. An NMOS circuit with the transistor biased to operate in the saturation region is shown in Figure 4.6(a). Using KVL around the drain-to-source loop gives  =  +     =



!

−

" # !

(4.1)

which describes the load line, and intersects the  -axis at  ⁄  and the -axis at  as shown in Figure 4.6(b).

Figure 4.6 NMOS with a small-signal input voltage $ The intersection of this load line with the  -  characteristic gives the operating (or quiescent) point for a given value of  . Let us assume that the drain current, drain-to-source voltage, and gate-to source voltage have initial quiescent values of  , , and  , respectively. In a MOSFET amplifier, an AC input signal is normally superimposed on the gate voltage. If a small AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Chapter 4

AC signal $% is connected in series with  , it will produce a small variation in the drain-tosource voltage   and the drain current  . That is, if the gate-to-source voltage varies by a small amount, such that   =  + $% , there will be corresponding changes in the drain current and drain-to-source voltage such that  =  + &% and   =  + & . This situation is shown in Figure 4. 6(b). The small variations of the drain current , as & , and the drain-to-source voltage  , as &% , around the operating point are shown in Figure 4.6(b). The drain-to-source variation  &% will equal the voltage gain times $% . If the values of & , $% , and &% are small, Figure 4.6(b) can be represented by the small-signal circuit shown in Figure 4.6(c). Therefore, we need two types of models for MOSFETs: a DC model and a small-signal model. The large-signal (DC) models of MOSFETs are nonlinear. The drain characteristics of  as a function of   for different values of  describe the large-signal model of a MOSFET. Since the gate-channel has an oxide layer, the gate current will be negligibly small. Thus, MOSFETs can be represented by the simple DC model of Figure 4.7.

Figure 4.7 Large-signal model of -channel MOSFETs The small-signal behavior of the MOSFET in Figure 4.7 can be represented by a small-signal AC equivalent circuit consisting of a voltage-dependent current source '( $% in parallel with an output resistance ) representing a finite slope of the -  characteristic. This circuit is shown in Figure 4.8(a). Since the gate current $ of MOSFETs is very small, tending to zero, the gate-tosource terminals are open circuits.

Figure 4.8 Small-signal model of MOSFETs Applying the relations between Norton’s and Thevenin’s theorems, we can represent the current source in Figure 4.8(a) by a voltage source, as shown in Figure 4.8(b). We find &% from &% = & ) − )'( $% = & ) − *$ $% (4.2) where *$ is the open-circuit voltage gain of the MOSFETs and is given by AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Chapter 4

*$ = ) '(

(4.3)

The circuits of Figure 4.8[(a) and (b)] are referred to as the Norton and Thevenin circuits, respectively, and they are equivalent. ) is the small-signal output resistance, and '( is the transconductance gain of the MOSFET. Their values are dependent on the operating point and are quoted at a specified operating point ( ,  ). The small-signal output resistance is the inverse slope of the  - characteristic in the pinchdown or saturation region. The output resistance ) is given by +

,-

=

&.

&" #

=

/ |1 |

= 2 for all MOSFETs

(4.4)

and 2 =⁄ 13 | is called the Here 3 is called the . The parameter 3 is positive for a -channel device and negative for an channel device. Its typical magnitude is 100 V. 3 is analogous to the Early voltage 4 of bipolar transistors. The trans-conductance is the slope of the transfer characteristic ( versus ) and is defined as the change in the drain current corresponding to a change in the gate-to-source voltage. It is expressed by 5 ' ( =  6 " #78)9%:9 5 Assuming  ≈ ,   ≈ , and  ≈  , the small-signal trans-conductance of an NMOS is given by '( =

;.

;" 9  −   = '() ?1 −

 9  −   These equations can be written in the form of a ratio as 'R( 4>9R  −  R 4>9 = = >9   −  R 1  which, for '( = 1 JK⁄  and  = 2JK, gives >9 = 125 *K⁄ R . The ratio S⁄ T can be found as 2 × 125 × 10 WX S 2>9 = = W[ = 11.8 T *: U)V 600 × 3.54 × 10 Assume T = 10*J; then S = 118*J . Also assume |3 | = 1⁄ 2 = 200and 2 = 5JW+. Then NMOS 2N4351 can be specified in PSpice/SPICE by the following statements: M1 ND NG NS NB M2N4351 .MODEL M2N4351 NMOS (KP=125U VTO=2.24 L=10U W=118U LAMBDA=5M) The MOS transistor has a length of 0.6*Jat minimum and can be expanded by integer increments of 0.3*J. The minimum width is 0.9*Jand can be expanded by integer increments of 0.3*J. Generally, attributes of an NMOS are T = 6GH10*J, S = 118*J, K^ = 720GH283.2*J, K` = 720*J, a^ = 302.4GH120.4*J, and a` = 302.4GH120.4*J. Generally, K` = K^ = 2.4*J × S, and a` = a^ = 2.4*J + S. The amplifier in Figure 4.6(a) has  = 2,  = 15, and  = 3.5bc. The NMOS parameters are  = 1 , >9 = 3.25 JK⁄ R , and 3 = 1⁄ 2 = 100. (a) Find the DC biasing point  , , and  . (b) Find the small-signal transistor model parameters ) and '( (c) Find the small-signal amplifier parameters ., ), and K ") AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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Chapter 4

November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

(d) Use PSpice to plot the small-signal AC output voltage for 1-mV sinusoidal input signal at 1 kHz. The NMOS parameters are >a = 6.5d, PQ = 1, T = 1f, S = 1f,and TKdg^K = 0.01. Note: PSpice uses > = >( = 2>9 . Solution a >( = > = 6.5 × 10Wi for S = T.   = >9  −  R = 3.25 × 10Wi 2 − 1 = 3.25JK  =  −   = 15 − 3.5 × 10i × 3.25 × 10Wi = 3.625 b ) = 3 ⁄  = 100⁄ 3.25 × 10Wi = 30.77bc '( = 2 × >9 −  = 2 × 3.25 × 10Wi × 2 − 1 = 6.5 JK⁄  c ) = )‖ =m30.77b‖3.5b = 3.143bc m n() = '( = 6.5 JK⁄  K") = −'( × ) = −6.5 JK⁄ × 3.143bc = −20.426 ⁄  d Figure 4.10(a) shows the PSpice schematic and the PSpice plot for small-signal output voltage is shown in Figure 4.10(b). The capacitor UR blocks the DC and passes the smallsignal output, which shows a voltage of -19.84; this is close to the calculated value of -20.42.

Figure 4.10 (a) PSpice schematic

(b) plot of small-signal output voltage for example 4.1

Complementary, or CMOS, circuits use both -channel and -channel enhancement-type MOSFETs in the same circuit. Because of their very low power consumption, CMOS circuits are commonly used in ICs. A CMOS inverter is shown in Figure 4.11(a). Transistor MP is a -channel device, and transistor MN is an -channel device. Each substrate is tied to its source. The input signal is connected to both transistor gates, and the output terminal is common to both drain terminals. The load characteristics of two CMOS devices are shown in Figure 4.11(b) for two extreme inputs: / = 0 and / = . For  / = 0, MN is off and its drain current is zero. MP has the characteristic corresponding to  =  . For / =  , M P is off and its drain current is zero. MN has the characteristic corresponding to  = . Thus, their drain currents are zero at these inputs, and the current drawn from the supply is zero.

AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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Chapter 4

November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Figure 4.11 CMOS inverter As the input voltage / is varied from zero to the maximum value DD , the output voltage O falls from DD to zero. The transfer characteristic is shown in Figure 4.11(c). Depending on the input voltage / , the VTC can be divided into five regions.

In region I, 0 ≤ / ≤  , where  is the threshold voltage of transistor M N. Since  = / < , M N remains off. At a low value of / ,  =  − / is high and positive. MP is turned on, and it is driven into the non-saturation (ohmic) region. Since the channel resistance of the offtransistor M N is very much greater than that of the on-transistor MP and since M N and MP form a voltage divider, the output voltage is  p ≈  , as shown in Figure 4.11(c). The various voltages are  = / ,  = − + /, and p =  .

In region II,  ≤ / ≤ 3 = / Gq1 and  = − + /  <  , where  is the threshold voltage of transistor MP and /Gq1 will be defined below. As / becomes greater than or equal to , MN conducts and operates in the saturation region, for which  is described by  <  = /  <  +  .

For  <  , MP remains in the ohmic region. With MN in the saturation region and MP in the ohmic region, the two drain currents must be equal; that is,  =  . Applying the expressions for the saturation and ohmic regions gives >9   −  R = > r2 +  −  Rs where >9 and > are the constants for -type and -type transistors, respectively. Substituting = / ,  =  − / , and  =  − p into the above equation, we get the relationship between / and  p as (4.9) >9 / −  R = > r2 − / +   − p  −  − p Rs /t can be found by differentiating Eq. (4.9) and setting up⁄ u/ = −1 to solve for  / = /t . If I is increased further,  increases and  decreases. Both M N and MP operate in the saturation region. At the transition point from the ohmic to the saturation region for MP , we get  =  −  Substituting the values for  =  −  / and   =  − p, we get AdU, CET, Department of Electrical and Computer Engineering By Hailay Berihu (M.Sc.)

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November 2015 Microelectronic Devices & Circuits (ECEg4261) Class Notes

Chapter 4

 − / =  − p −  which gives the input voltage at the first transition as /Gq1 = / = p +  The corresponding output voltage is pGq1 = p = / −  whose plot is a straight line that intercepts the output axis at − (a positive quantity), as shown in Figure 4.11(c). The intersection with the transfer characteristic gives /Gq1 and pGq1. To solve for the value of / Gq1 or p Gq1, one of these quantities must be known. In region III, / = / Gq1. Both M N and MP operate in the saturation region. Since the two drain currents must be equal, =  , or >9   − R = >  +  R Substituting   = / and  =  −  / , we get the input voltage at the transition of MP from the ohmic to the saturation region: / Gq1 = 3 =



 @v@w xyz ⁄yE +xyz ⁄yE

=

@v@w{y|



+{y|

(4.10)

which is independent of output voltage p . For identical transistors, >9 = > and  = ||, and Eq. (4.10) is reduced to / Gq1 = 3 =



R

(4.11)

which is desirable to maximize the noise immunity of the circuit. Once we determine the value of /Gq1 from Eq. (4.11), we can find the output voltage at the edge of the transition of MP from pGq1 = p = / Gq1 −  This segment ends when MN enters the ohmic region, which is defined by   =  +  Substituting   = / and  = p into the preceding equation yields / = p +  which gives the input voltage at the transition of MN from the saturation region to the ohmic region as / Gq2 = / = p +  The corresponding output voltage is given by p = / −  which intercepts the input axis at , as shown in Figure 4.11(c). The intersection with the transfer characteristic gives / Gq2and p Gq2. Since / Gq1 is independent of p and / = / Gq1 = / Gq2, the quantities pGq1 and p Gq2 must be different. There will be two transitions: the first for MP from the ohmic region to the saturation region at an output voltage of  p = / +  and then the second for MN from the saturation region to ...