PMOS DC characteristics PDF

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Summary

Notes and simulations on the DC characteristics of PMOS transistor...

Description

EXPERIMENT 2 AIM: To study the DC characteristics of p-MOS and find Vt, λ, γ and k.

SOFTWARE USED: LTspice XVII

THEORY: 1. Definition and physical structure Standing for P-channel Metal Oxide Semiconductor, NMOS is a is a microelectronic circuit used for logic and memory chips and in complementary metal-oxide semiconductor (CMOS) design. A PMOS transistor consists of 4 terminals: Source, drain, gate and substrate (usually the gate and substrate are connected together). The source and drain are of p-type material, and the substrate is of n-type material. The Gate with W and L dimensions is separated from the substrate by a dielectric (SiO2), creating a similar structure of the capacitor plates.

Figure 1: NMOS physical structure

If a negative voltage is applied to the gate, positive charges are induced (inversion layer) on the substrate surface and they create a conduction path between the drain and source terminals. The minimum voltage needed to create the inversion layer is called threshold voltage (V t). This is a characteristic feature of the transistor. If V GS< Vt, the drainsource current is zero. Typical values for this voltage are between 0.5 and 3 volts.

2. Operating regions The NMOS has 4 regions of operation: Region of operation Cut-off region Linear or Triode region

Description In this region |VGS| < |VTH| and the current ID = 0. In this region |V GS| ≥ |VTH| and |VDS| ≤ |VGS| – |VTH|, and the transistor behaves as a non-linear resistive element, controlled

Saturation region

by voltage. In this region |V GS| ≥ |VTH| and |VDS| ≥ |VGS| – |VTH|, and the

Breakdown region

transistor behaves as voltage controlled current source VGS. In this region the transistor by the avalanche phenomena in the drain and source terminals.

Figure 2: PMOS operating regions

CIRCUIT DIAGRAMS

Figure 3: Circuit diagram for PMOS transistor without substrate bias

Figure 4: Circuit diagram for PMOS transistor with substrate bias

OUTPUT 

Without substrate bias

Figure 5: PMOS transfer characteristics without substrate bias

Figure 6: PMOS output characteristics without substrate bias for multiple values of VGS

Figure 7: Output characteristics of PMOS without substrate bias for VGS = -1.8V



With substrate bias

Figure 8: Transfer characteristics of PMOS with substrate bias

Figure 9: Output characteristics of PMOS with substrate bias for multiple values of VGS

Figure 10: Output characteristics of PMOS with substrate bias for VGS = -1.8V

OBSERVATION TABLES

Table 1: Output observation table for PMOS (VGS = -1.8V)

VDS1 ID1 VDS2 ID2

VSB = 0V -1.2V -28.839μA -1.455V -30.022μA

VSB = 0.5V -1.264V -24.162μA -1.516V -25.132μA

Table 2: Transfer characteristics observation table for PMOS

VGS1 VGS2

VSB = 0V 2.116mA1/2 -1.114V 3.299mA1/2 -1.345V

VSB = 0.5V 1.507mA1/2 1.093V 2.954mA1/2 -1.376V

CALCULATIONS Table 3: Calculations table

Parameter Threshold voltage

Formula

VSB = 0V -1.459V

VSB = 0.5V -1.385V

Channel length 0.199V-1

modulation coefficient Transconductance

0.199V-1

26.229mA/V2 26.144mA/V2

Where: γ = 0.4

VTO = -0.7V

CONCLUSION Similarly to NMOS, the implementation of substrate bias increases the values of threshold voltage and transconductance parameters for PMOS, but the channel length modulation coefficient remains constant....