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International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016

Design and Analysis of Improved Performance Ring VCO based on Differential Pair Configuration Bhavana Goyal1, Shruti Suman2, P. K. Ghosh3 ECE Department, College of Engineering and Technology Mody University of Science and Technology Lakshmangarh, Sikar, Rajasthan, India [email protected], [email protected], [email protected] Abstract— Voltage controlled oscillators (VCOs) are the most important basic building block of wired or wireless communication systems where these are mostly used as high frequency clock generating subsystems. The main objective of this paper is to design a high frequency VCO with a good phase noise performance and low power consumption. This paper presents an improved performance CMOS voltage controlled ring oscillator which is based on single ended differential pair configuration. The performance parameters of VCO like frequency, tuning range and power dissipation are also analyzed here. The proposed single ended ring VCO is implemented using 180 nm CMOS technology and 3.5 V power supply. It provides a wide tuning range from 5.2996 GHz to 6.567 GHz at 0.5 V to 2.5 V control voltage variation with 2.921 mW to 6.806 mW power consumption. The simulation results satisfies basic concept of VCO in which oscillation frequency linearly varies with supply voltage. The implemented design has high oscillation frequency, and also consumes less area as compared to existing current starved ring VCO. Keywords—CMOS, VCO, Differential Pair, Current Starved, Ring Oscillator

I. INTRODUCTION The voltage controlled oscillator (VCO) is most fundamental building block of communication systems. In the VCO oscillation frequency is varied by a control voltage. It can be implemented using ring, relaxation, and LC resonant circuits. Ring structures are mostly used due to their ease of integration [1], less die area, speed and wide operating frequency range. Ring VCOs have a large number of applications including clock recovery phase-locked loops (PLL’s) for serial data communication [2], clock frequency multiplication [3], oversampling analog to digital converters etc. CMOS ring oscillators can be implemented either by differential or single ended delay stages. Differential circuits and signals provide a good rejection of common-mode supply and substrate noise while single-ended circuits have better thermal noise performance due to large voltage swings as compared to differential configurations. The voltage swings of differential ring oscillators are limited to approximately a threshold voltage. Single ended ring oscillators are susceptible to supply noise due to their single-ended signal path.

II. RING OSCILLATOR

Fig. 1. Linear model of three stage ring oscillator

A ring oscillator consists of three or more odd number of inverter stages in a negative feedback loop configuration. For oscillation, ring oscillator must satisfy the Barkhausen criteria [4], [5]. The oscillation period of ring oscillator corresponds to the time it takes a transition to propagate twice around the loop. For delay ( t d ) of a single inverting stage the frequency of oscillation ( fosc ) for N number of identical stages can be calculated as:

f osc =

(1)

1 2 Nt d

Hence the oscillation frequency of an N-stage ring oscillator can be tuned by varying the time delay of each stage [6]. Open loop transfer function which is determined by small signal gain of each delay stage ( g m ), load resistance (R) and capacitance (C) at the output of each stage, is given by linear model shown in Fig. 1 can be given as:

§ − gmR · H ( j ω) = ¨¨ ¸¸ © 1 + RjωC ¹

(2)

3

According to Barkhausen criteria for oscillation the frequency dependent phase shift of three stage ring oscillator must be equal to 180° i.e. each delay stage should contribute 60° phase shift [7]. The magnitude of the loop gain at oscillation

978-1-4673-9939-5/16/$31.00 ©2016 IEEE

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frequency ( ωosc ) must be greater than or equal to unity which is given by equation (3) and (4) as:

tan − 1 (ω osc RC ) = 60 ο

(4)

(g mR )3

(1 + (ω

osc

RC )

(3)

2

Here

g m3 is the transconductance of transistor M 3 , ro2 and

ro4 are the drain to source resistances of transistors

M 2 and

M 4 respectively.

B. High Frequency Analysis of Differential Pair

≥1

3 2

)

Therefore voltage gain for each stage must be greater than or equal to two as (5)

gm R ≥ 2 III. P ROPOSED RING VCO

Proposed delay cell is based on differential configuration pair with active load. To convert differential output to single ended output, active load is used in differential pair. A. Differential pair with single ended output: A differential pair with single ended output is shown in Fig. 2. Here the transistors M1and M2 form a differential pair which has a current mirror as load formed by transistors M3 and M4. The drain current of M1 is fed to the input transistor of the mirror M3 thus same current I / 2 will flow through the M4 transistor. Common mode rejection ratio for this amplifier is given as:

[

]

CMRR = g m ( ro 2 ro 4 ) [2g m3 Rss ]

(6)

Fig. 3. Differential pair with capacitances which have high impact on frequency

The Fig. 3 shows the differential pair configuration with two parasitic capacitances CA and C B , which have high impact on frequency response. Here CA and C B represents the total capacitance at the input node of the current mirror and total capacitance at the output node respectively. That is,

C A = C gd1 + C db1 + C db3 + C gs3 + C gs4

(7)

C B = C gd2 + C db2 + C gd4 + Cdb4 + C x

(8)

Here C x is the input capacitance of a subsequent stage. For frequency analysis of this circuit the high frequency small signal model is shown in Fig. 4. The circuit can be replaced by Thevnin equivalent as shown in Fig. 5. Assuming g m1 = g m2 = g mn gm 3 = gm 4 = gmp , ro1 = ro2 = ron and ro3 = ro4 = rop . The Thevnin voltage ( Vt ) and Thevnin resistance ( Rt ) are given by equations (9) and (10): (9)

Vt = g mn ron (V1 − V2 ) Fig. 2. Differential pair with single ended output

(10)

R t = 2ro

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Also, output voltage can be given as

V O = −Z B (1 + g mpZ A )I

(15)

After putting the value of threshold voltage ( Vt ) from equation (9) into equation (14) the current can be given as equation (16)

I=

g mnron (V1 − V 2 ) Z A + Z B + R t + g mp Z A Z B

(16)

Now from equation (15) and (16), Voltage gain in sdomain AV ( s) is

Fig. 4. High frequency small-signal equivalent model for differential pair

AV (s ) =

gmn ron rop ( 2 gmp + sC A ) 2 ron rop CA CB s + CA( rop + 2 ron ) + rop(1 + 2 gmp ron )

[

2

]

(17) Assuming the transfer function has two real poles, so general form of voltage gain can be written as

AV (s ) = AV 0

Here

§ s · ¨¨ 1+ ¸ ω Z ¸¹ © ·§ § ¨1 + s ¸ ¨1 + s ¨ ω p 1 ¸¹ ¨© ω p 2 ©

ωZ denotes

(18)

· ¸ ¸ ¹

frequency of zero andω p1 ,

ω p 2 are

real

poles. Comparing Equations (17) and (18) ,we get

Fig. 5. Simplified small-signal model for differential pair

The impedances Z A and Z B are given by equations (11) and (12) as

ZA =

ZB =

(g

1 mp + sC A )

rop

(1 + r

AV 0 ≅

1 + 2 g mp (ron +rop )

(11)

ωZ ≅ (12)

ω p1 ≅

C Bs )

On summation of all voltages around the loop in Fig. 5, we have

ω p2 ≅

(13) Here

Here

V t = Z A I and after solving we get current (I) as I=

Vt Z A + Z B + Rt + g mp Z A Z B

(r

2 gmp CA

(20)

1

(21)

on

op

(Z A + Z B + Rt )I + g mpZ BV3 + Vt = 0

(14)

(19)

2 gmn gmp ron rop

ωz ≅ ω T

and

)

rop CB (22)

gmp CA

ω p 2 ≅ ωT 2

where

ωT is the

transition frequency at which the magnitude of the high frequency current gain of the MOSFET becomes unity. For shorter devices transition frequency is in the range of GHz . Transition frequency ( ωT ) of NMOS transistor can be determined by equation (23)

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ωT ≅

1.5μ nVOV L2

(23)

C. Proposed Delay Cell

Fig. 7. Proposed three stage ring VCO

Fig. 6. Proposed delay cell

Proposed delay cell is based on differential pair with active load as shown in Fig. 6. This delay cell is same as differential pair shown in Fig. 2 except that it does not have any tail current source and hence same frequency analysis given in section B can be done for this delay cell. Here transistor M 2 works as a core inverter which has transistor M 4 as active load. Transistor M 4 is biased with inverter scheme of transistors M1 and M 3 from control voltage ( Vctrl ). Gain of delay cell changes with the variation of control voltage (V ctrl ). This delay cell has advantages of both differential and single ended configuration because differential amplifier has fast oscillation frequency and single-ended output amplifier has high output voltage swing. Proposed delay cell drives only single gate so less capacitance present at the output as compared to conventional delay cell which results in high operating speed. Here common node voltage of output is not constant due to absence of tail current source. IV. S IMULATION RESULTS The proposed three stage ring VCO is designed and simulated at 180 nm CMOS technology and power supply of 3.5 V for different value of control voltages which is shown in Fig. 7. The corresponding output waveform of the circuit is shown in Fig. 8. Table I includes the summarized simulation results which shows the approximate linear variation of frequencies and power consumption with control voltages.

Fig. 8 Output waveform of proposed ring VCO TABLE I: SIMULATION RESULTS OF PROPOSED THREE STAGE RING VCO AT DIFFERENT CONTROL VOLTAGES Control Voltage (V)

Oscillation Frequency (GHz)

Power Consumption (mW)

0.5 1.0 1.5 2.0 2.5

5.299 5.782 6.013 6.234 6.567

2.921 5.159 6.405 6.691 6.806

Fig. 9. Layout of proposed three stage ring VCO

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Fig. 9 depicts the layout design of proposed three stage ring VCO at 180 nm CMOS process which occupies total area of 2 31.808 μm . Comparative analysis of three stage conventional current starved ring VCO [8] and proposed ring VCO at 180 nm CMOS technology with 2.5 V control voltage is done in table II. From the table it can be concluded that proposed circuit provides higher oscillation frequency and less area than conventional current starved ring VCO. TABLE II: COMPARATIVE ANALYSIS OF THREE STAGE CONVENTIONAL CURRENT STARVED AND PROPOSED RING VCO Conventional Current Starved Ring VCO

be achieve by increasing control voltage. Comparative analysis in table II shows the proposed circuit provides higher oscillation frequency and less area than conventional circuit. Thus, this circuit is much useful for high frequency applications.

References [1]

C.-H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6-_m CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 586–591, May 1999.

[2]

A. W. Buchwald, K. W. Martin, A. K. Oki, and K. W. Kobayashi, “A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction Fig. 7. Measured closed-loop jitter of 622 MHz PLL. bipolar transistors,” IEEE J. Solid-State Circuits, vol. 27, pp. 1752–1762, Dec. 1992. M. Horowitz, A. Chan, J. Cobrunson, J. Gasbarro, T. Lee, W. Leung, W. Richardson, T. Thrush, and Y. Fujii, “PLL design for a 500Mb/s interface,” in ISSCC Dig. Tech. Papers, pp. 160–161, Feb. 1993.

Proposed Ring VCO [3]

Frequency ( GHz )

3.425

6.567

Power Consumption ( mW )

4.341

6.806

[4]

J. M. Rabaey, “Digital integrated circuits: A design perspective,” Prentice- Hall Book Company, 1st edition, ISBN No. - 0-13-178609-1, 1996.

No. of Transistors used in Three Stage Ring VCO

14

8

[5]

Layout Area (μm 2)

71.167

31.808

Shruti Suman, Monika Bhardawaj & Prof. B. P. Singh, “An Improved performance Ring Oscillator Design”, in International Conference on Advance Computing and Communication Technology, Rohtak, India, IEEE digital library, pp. 236-239, Jan. 2012.

[6]

B. Razvi, Design of Analog CMOS Integrated Circuits, Tata McGrawHill, Third edition, 2001.

[7]

Bhawika Kinger, Shruti Suman, K. G. Sharma and P. K. Ghosh “Design of Improved Performance Voltage Controlled Ring Oscillator” 5th IEEE International Conference on Advanced Computing &Communication Technologies, Rohtak, (India), IEEE Digital library, ISBN No. 978-1-4799-8487-9, pp. 441-445, Feb. 2015. Gudlavalleti Rajahari, Yashu Anand Varshney, and Subash Chandra Bose, “A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator”, SpringerVerlag Berlin Heidelberg CCIS 382, pp. 10–18, 2013.

V. C ONCLUSION The three stage high frequency ring VCO has been designed and simulated using 180 nm CMOS technology. Various design parameters such as frequency, power consumption and area are analyzed. High frequency analysis shows that single ended output delay stage provides better frequency stability than that for differential output delay stage. The simulation results in table I show that the higher oscillation frequency can

[8]

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