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Sequence Detector using Moore FSM

Team Members Details: Abstract : A state-machine is the one which detects the transition from one state to another state any number of times. The Moore FSM here in this mini-project detects only when a specific sequence is obtained in the sequence such as “1011”. The Moore FSM output depends on only the current state of the FSM. Thus the present state and the next state are noted. This verilog mini project depicts the detection of a sequence using a verilog code. Literature Survey : (Papers/any other material referred for the problem statement and design) A Moore State Machine was designed using a sequential circuit design for the detection of the sequence “110”. This implementation was made using J-K flipflop using a VHDL code [1]. Later implementation of the same sequence detector was done using Mealy FSM which was also implemented on the Xilinx platform whose code was also written in VHDL [2]. An implementation for the Moore sequence detector using all the sequential and combinatorial circuits was implemented. No language was used[3]. Another implementation of the FSM is done using D Flipflop which was implemented using a circuit diagram[4]. Problem Statement with Specifications: Design of a Moore Finite State Machine to detect the particular sequence by searching it in the states present in the state machine. Features / Specification:  Detects any sequence in the state machine.  Designed using sequential circuits.  May be synchronous or asynchronous.  Outputs determined solely by the current state  Outputs are unconditional (not directly dependent on input signals) Objective: (Preferably in points) The following objectives are to be achieved with the implementation:  Detection of any sequence in the state machine.  Transition from any state to any state.

 Display the detected sequence with a bit high. Theory: State diagrams are used to graphically represent state machines. At the dataflow level, where we separate control and data of hardware system, the design and description of state machines for implementing the control unit become important. The general architecture of an FSM consists of a combinational block of next state logic, state registers, and combinational output logic. There are two types of state machines - Moore machines and Mealy machines. As we have mentioned before "Moore" is less. That is, Moore machine's output depends on state variables only not on inputs. Mealy machine's output depends on both inputs and state variables. We called Moore machine's output function "state-based". Output function of the Mealy machine is called input-and-state-based. Graphically a "state-based" FSM looks like:

Fig 1. General Block diagram of FSM

A Sequence Detector: A sequence detector is a process where in the states in the finite state machine are changed by giving the inputs such as 1 or 0. As a result, when the corresponding sequence required is obtained, it is popped out and displayed it to the user. Suppose that we have a FSM shown in the figure below:

Fig 2. Moore FSM Diagram

Suppose that the sequence to be detected is 101. In the above diagram, initially the starting point is A. the input is 1, it moves to point B, if input is 0, it remains at B. Now if the input is 1, the

state changes from B to C. The output sequence that is obtained is 101 and thus it is detected. Methodology: The Arithmetic and Logic implementation is implemented in steps as follows:  Initially FSM is studied thoroughly.  Feasibility study is done so as what type of detection is to be implemented, how it is to be implemented, which software is to be used, etc.  Literature survey is done so as to identify the sources of previous implementations, their methods and the results obtained.  Once the feasibility study is done, components on what has to be implemented in the Moore’s FSM sequence detector is decided.  The verilog code is written for the Moore FSM sequence detector.  The written verilog code is implemented on the Xilinx Platform and then simulated.

Fig 3. Methodology Diagram

Program:

Sample Test cases: Case 1: 1011 Case 2: 101 Case 3: 011 Simulation Results: For Case 1: 1011

For Case 2: 101

For Case 3: 011

Synthesis view:

Analysis of the result obtained: Case 1: The input detection sequence given to the Moore FSM sequence detector is 1011. The corresponding sequence is detected and the output of FSM is shown high. Case 2: The input detection sequence given to the Moore FSM sequence detector is 101. The corresponding sequence is detected and the output of FSM is shown high. Case 3: The input detection sequence given to the Moore FSM sequence detector is 011. The corresponding sequence is detected and the output of FSM is shown high. Learning Outcomes: The following points were learnt:  Reviewing the papers, its implementations, advantages and drawbacks and chalking it out was studied.  Feasibility study, i.e. choosing the software, language for the implementation was learnt.  Code design using verilog and debugging it during an occurrence of error was learnt.  Code Implementation for the Moore FSM sequence detecor using Xilinx and simulation result analysis was studied.  The representation of the whole process as a report was being studied. References : [1] “Sequence Detector using Mealy and Moore State Machine VHDL: Source: allaboutfpga.com [2] Sequence Detector, Source: https://www.ee.iitb.ac.in [3] Moore “01010” sequence detector. Source: https://electronics.stackexchange.com [4] Design Moore sequence detector to detect a sequence 101-using DF/F. Source: http://www.ques10.com [5] Mealy and Moore Machines, Joel Schipper, University of Florida,2007...