Lab2 - Lab Report PDF

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NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York SUMMER, 2019

Component and Subsystem Design II CET 4805 SECTION D485 Meeting Day: Tuesday thru Thursday INSTRUCTOR: Prof. Y. WANG STUDENT: Urgiles, Cristhian

Design Decoders and Programming a FPGA Submission Date 07/22/2019

Lab Objective To familiarize oneself with 7-segment decoder module to display a character on a 7segment display using different VHDL code approaches. The 7-segment decoder module has a four-bit input d3d2d1d0. This decoder produces seven outputs that are used to display a character on a 7-segment display. The seven segments in the display are identified by the indices 0 to 6 shown in the figure. Each segment is illuminated by driving it to the logic value 0 (At DE2, SevenSegment LED Display Decoder with Active-LOW Outputs).

Figure 1- Seven Segment Decoder The equipment used was the Altera Cyclone II FPGA, with an EP2C35F672C6 chip, Quartus II software and a computer.

Lab Overview In this lab we design a BCD-to-7 segment decoder using 4 VHDL code approaches. After successfully testing the decoder on the DE2 board, we’ll have to redesign the decoder to display a set of given characters, which will make use of all 16 hexadecimal values. We will then apply the new design to any of the given approaches and create our own VHDL code where we will combine all codes. Lastly, we are to use Port Map Instantiation to implement the codes from the previous approaches. Overall there are four parts to this lab.

Lab Implementation 1.

The first part of the lab consists of designing a BCD-to-Seven Segment Decoder. We assign a bus value using D3, D2, D1, and D0 to represented each bit position in a 4-bit bus D (also represented by D[3…0] in the VHDL file). Similarly, the outputs will be represented by a 7-bit bus, S[6..0], as shown in the Truth table below (figure xx). Assuming the buses are properly defined in the Entity Declaration, we can say that bus S will take on the 7-bit value that corresponds to the value of bus D. a. First, we create a new project: i. Open the Quartus II software. Select File – New Project Wizard. Enter the appropriate drive letter for the designated storage area on the computer you are using followed by the working directory C:\My Desktop\CET4805\Lab2_1. Assign the project name DesignDecoder, assign Cyclone II for the device family, and select the EP2C35F672C6 chip in the Family & device settings. b. Then, we create a VHDL file (bdf): i. Open a new VHDL Device Design file (File > New) by highlighting VHDL File. Type the VHDL codes shown in Text Box.

ii.

iii.

iv.

File name vhdl2_1.vhd must be chosen according to which approach is being used. Save the VHDL file as vhdl2_1.vhd as part of our project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save. Select File > Create/Update > Create Symbol Files for Current File to create a symbol file for the VHDL code entered. A display window should soon appear stating that the Create Symbol File was (or not) successful. Click OK and close the Compilation Report window. Open a new Schematic file (File > New) by highlighting Block Diagram/Schematic File. And click OK. And construct the circuit shown in Figure 2 using the symbols you just created. Each symbol should be available in the Project Library in the Symbol diagonal box.

Figure 2 Symbol for VHDL_2_1 v.

Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as Decoder.bdf. Place a check mark in the space labeled Add file to current project and press Save. vi. Compile the project by selecting Processing > Start Compilation, or press Ctrl-L, or use the Compilation button in the toolbar. The compilation takes several seconds. When it is complete it should give a message that indicates, “Full compilation was successful”. Press OK. If unsuccessful, correct all errors and try to re-compile. c. Simulate a Vector Waveform File (vwf) i. We create a Vector Waveform File (vwf) to simulate a design(bdf) file. Add all inputs and output, specify an end time of 20 µs for our waveform display, and then save it as Decoder.vwf. ii. When creating the D[3..0] bus, enter D for the bus name, select Hexadecimal for the Radix, and enter 4 for the Bus Width in the Node Properties window. When created, the D waveform will appear with a plus sign implying that it can be ungrouped to show the individual bits, D[3], D[2], D[1], and D[0]. iii. Select Processing – Start Simulation, or press Ctrl-I, or use the Simulation button in the toolbar. After a few moments a message stating, “Simulation was successful” should appear. Click OK.

iv.

The Simulation Waveforms appear in the Simulation Report. You may have to expand the size of the Simulation Waveforms to suit your need and choose View > Fit in Window to see the entire waveform as in figure 3.

Figure 3- Simulation Waveform

Code

Code creates a logic vector of 4 inputs (D) and 7 outputs (S) using the When/ Else approach (1st approach).

Pin Assignment Pin Assignment of Inputs (D) and outputs (S).

Analysis for Simulation Based on our simulated waveform, when inputs D1, D2, D3 are Low and input D0 is high, the resulting S1 and S2 outputs are turned on since the DE2 board has Active-Low outputs. Meanwhile every other output is off, High. This displays in the number “1” on our 7-segment display. This analysis applies to the rest of the inputs and their corresponding outputs.

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Configuration for FPGA Device (JTAG)

Truth Table

2.

Symbol

D3

D2

D1

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D0 Shape S6 S5 S4 S3 S2 S1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 2 3 4 5 6 7 8 9 A b C d E F

1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0

0 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0

0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0

0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1

0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1

0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0

The second part of the lab consists of creating a truth table with negative logic to convert binary to hexadecimal that includes the 16 characters of A, b, C, d, E, F, g, H, I, L, O, P, q, s, U, and blank (the ‘blank’ character, which is selected for codes 0000 − 1111). a. First, we create a new project: i. Based on the truth table we create a VHDL entity for the 7-segment decoder. Our VHDL program has a 7-bit output with a 4-bit input.

b. Connect the d3d2d1d0 inputs to switches SW3, SW2, SW1, SW0, and connect the outputs of the decoder to the HEX0 display on the DE2 board. The segments in this display are called HEX00, HEX01, … , HEX06, corresponding to Figure 1. We declare the 7-bit port in your VHDL code: HEX0 : OUT STD LOGIC VECTOR(0 TO 6); 6. c. After making the required DE2 board pin assignments, compile the project.

d. Download the compiled circuit into the FPGA chip. e. Design the test table based on the requirement of the subsystem. Test the functionality of the circuit by toggling the SW3−0 switches and observing the 7-segment display.

Code

Code creates a logic vector of 4 inputs (D) and 7 outputs (S) using the When/ Else approach (1st approach).

Pin Assignment

The pin assignment is the same as the one used in part 1 of the lab.

Truth Table

3.

Symbol

D3

D2

D1

A B C D E F G H I L O P Q S U

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D0 Shape S6 S5 S4 S3 S2 S1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Blank A b C d E F g H I L O P q S U

1 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1

1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0

1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0

1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0

1 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0

1 0 1 1 0 1 1 0 0 0 1 0 0 0 1 0

1 0 1 0 1 0 0 0 1 1 1 0 0 0 0 1

In part 3 of this lab, we viewed different approaches to designing a 7-segment display with our DE2 board. The approaches include vhdl2_1.vhd, vhdl2_2.vhd, and vhdl2_3.vhd, and vhdl2_4.vhd a. Design the decoder vhdl2_4.vhd (approach 4) by using if-elsif-else statements in VHDL and create a symbol file (Select File > Create/Update > Create Symbol Files for Current File to create a symbol file for the VHDL code entered). b. Open the schematic file Decoder.bdf, Place four components in one design entry as followings (each schematic is generated from vhdl designed with four different approaches) c. Simulating a Vector Waveform File

d. Making the required DE2 board pin assignments, compile the project. e. Download the compiled circuit into the FPGA chip. f. Design the test table based on the requirement of the subsystem. Which was used

Code

Second Approach Code- with/select

Third Approach Code- case/when statement

Fourth Approach Code- If/Else

Pin Assignment

Analysis for Simulation

4.

The last part of the lab we had to present the bdf schematic as a VHDL code. a. Open a new VHDL Device Design file (File > New) by highlighting VHDL File. And click OK. Type the VHDL code Decoder.vhd and save the file as a top entity of your project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save b. Combine them together (top entity and component) Decoder.vhd (top entity), vhdl2_1.vhd (component), vhdl2_2.vhd (component), vhdl2_3.vhd (component), vhdl2_4.vhd (component) and refer to schematic to make the system design c. Pin configuration (the same configuration as PART III is used) d. Download your design into FPGA board and test.

Code

Conclusion In this lab, we explored the 7-segment decoder module. The module has the four-bit input d3d2d1d0, produces seven outputs that are used to display a character on a display. Each segment is illuminated by driving it to the logic value 0. We used VHDL code different approaches using different functions namely, when/else, with/select, case/when and if/else statements for decoder that implements logic functions that represent circuit needed to activate each of the seven segments. We connected the d3d2d1d0 inputs to switches SW3, SW2, SW1, SW0, and the outputs of the decoder to the HEX0 display on the DE2 board and assigned the pins to DE2 board. After that we compiled circuit into the FPGA chip, designed the test table based on the requirement of the subsystem and tested the functionality of the circuit by toggling the switches. Our experiment was as a success, as we our truth table matched the results we obtained from the DE2 board....