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SOLUTIONS MANUAL M. MORRIS MANO

COMPUTER SYSTEM ARCHITECTURE

Third Edition

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Solutions Manual

Computer System Architecture

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TABLE OF CONTENTS

Chapter 1 ……………………………………………………………………………… 4 Chapter 2 ……………………………………………………………………………… 11 Chapter 3 ……………………………………………………………………………… 16 Chapter 4 ……………………………………………………………………………… 20 Chapter 5 ……………………………………………………………………………… 26 Chapter 6 ……………………………………………………………………………… 34 Chapter 7 ……………………………………………………………………………… 45 Chapter 8 ……………………………………………………………………………… 51 Chapter 9 ……………………………………………………………………………… 59 Chapter 10 ……………………………………………………………………………. 63 Chapter 11 ……………………………………………………………………………. 80 Chapter 12 ……………………………………………………………………………. 89 Chapter 13 ……………………………………………………………………………. 95

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CHAPTER 1

=

1.1 ABC

A•B•C

(A•B•C)'

A'

B'

C'

A'+B'+C'

000 001 010 011 100 101 110 111

0 0 0 0 0 0 0 1

1 1 1 1 1 1 1 0

1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

1 1 1 1 1 1 1 0

1.2 ABC 000 001 010 011 100 101 110 111

A⊕ B 0 0 1 1 1 1 0 0

A⊕B ⊕C 0 1 1 0 1 0 0 1

1.3 (a) (b) (c) (d)

A + AB = A(1 + B) = A AB + AB' = A(B + B') = A A'BC + AC = C(A'B + A) = C(A' + A) (B + A) = (A + B)C A'B + ABC' + ABC = A' B + AB(C' + C) = A'B + AB = B(A' + A) = B

1.4 (a) (b)

AB + A (CD + CD') = AB + AC (D + D') = A (B + C) (BC' + A'D) (AB' + CD') =

1.5 (a) (b) 1.6 (a)

(b) (c)

ABB'C' A'AB'D BCC'D' A'CD'D + + + =0 0 0 0 0

(A + B)' (A' + B') = (A'B') (AB) = 0 A + A'B + A'B' = A + A' (B + B') = A + A'= 1

F F'

= x’y + xyz’ = (x + y') (x' + y' + z) = x'y' + xy' + y' + xz + y'z = y' (1 + x' + x + z) + xz = y'+ xz F•F' = (x'y + xyz') (y' + xz) = 0 + 0 + 0 + 0 = 0 F + F' = x'y + xyz' + y' + xz (y + y') = x'y + xy(z' + z) + y' (1 + xz) = x'y + xy + y' = y(x' + x) + y' = y + y' = 1

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1.7 (a) xyz 000 001 010 011 100 101 110 111

F 0 1 0 0 0 1 0 1

(c) F = xy'z + x'y'z + xyz = y'z(x + x') + xz(y + y') = y'z + xz

(d) Same as (a)

1.8 (a)

(b)

(c)

(d)

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1.9 (a)

(b)

(c)

(d)

1.10 (a)

(1) (2) 1.11

(b)

F = xy + z' F' = x'z + y'z F = (x + z’) (y + z')

(1) (2) (a)

F = AC' + CD + B'D F = (A + D) (C' + D) (A + B'+C) (b)

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1.12

1.13 (a) F = x'z' + w'z (b) = (x' + z) (w' + z')

1.14 S = x'y'z + x'yz' + xy'z' + xyz = x'(y'z + yz') + x(y'z' + yz) = x'(y ⊕ z) + x(y ⊕ z)' =x ⊕ y ⊕ z

1.15 xyz 000 001 010 011 100 101 110 111

See Fig. 1.2 (Exclusive - NDR)

F 0 0 0 1 0 1 1 1

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1.16 xyz ABC 000 001 001 010 010 011 011 100 100 011 101 100 110 101 111 111 c = z' By inspection

1.17 When D = 0; J = 0, K = 1, Q → 0 When D = 1; J = 1, K = 0, Q → 1

1.18 See text, Section 1.6 for derivation.

1.19 (a)

DA = x'y + xA; DB = x'B + xA; z = B

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(b) Present state AB

Inputs xy

Next state Output AB z

00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11

00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

00 10 00 00 01 11 00 00 00 10 11 11 01 11 11 11

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

1.20

1.21 Count up-down binary counter with table E Next Flip-flop Present Inputs state state inputs AB EX AB JA KA JB KB 00 00 00 0X 0X 00 01 00 0X 0X 00 10 11 1X 1X 00 11 01 0X 1X 01 00 01 0X X0 01 01 01 0X X0 01 10 00 0X X1 01 11 10 1X X1 10 00 10 X0 0X 10 01 10 X0 0X 10 10 01 X1 1X 10 11 11 X0 1X 11 00 11 X0 X0 11 01 11 X0 X0 11 10 10 X0 X1 11 11 00 X1 X1 -9-

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CHAPTER 2 2.1 TTL JC 12/2 = 6 gates 7404 12/3 = 4 gates 7486 12/4 = 3 gates 12/5 = 2 gates 7421 12/6 = 2 gates 74260 1 gate 7430 12/6 = 2 FFs 74107

(a) (b) (c) (d) (e) (f) (g)

Inverters – 2 pins each 2-input XOR – 3 pins each 3-input OR – 4 pins each 4-input AND – 5 pins each 5-input NOR – 6 pins each 8-input NAND – 9 pins JK flip-flop – 6 pins each

2.2 (a) (b) (c) (d)

74155 – Similar to two decoders as in Fig. 2.2. 74157 – Similar to multiplexers of Fig. 2.5. 74194 – Similar to register of Fig. 2.9. 74163 – Similar to counter of Fig. 2.11

2.3

2.4

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2.5 Remove the inverter from the E input in Fig. 2.2(a). 2.6

If all inputs equal 0 or if only D0 = 1: the outputs A2A1A0 = 000. Needs one more output to recognize the all zeros input condition.

2.7

2.8 S1 S0 0 0 0 1 1 0 1 1

YA YB A0 B0 A1 B1 A2 B2 A3 B3

Function table

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2.9

When the parallel load input = 1, the clock pulses go through the AND gate and the data inputs are loaded into the register when the parallel load input = 0, the output of the AND gate remains at 0. 2.10 The buffer gate does not perform logic. It is used for signal amplification of the clock input. 2.11

One stage of Register Fig. 2.7

Load 0 0 1

Clear 0 1 x

D Q(t) 0 I0

Operation no change Clear to 0 load I0

Function table 2.12

2.13 Serial transfer: One bit at a time by shifting. Parallel transfer: All bits at the same time. Input serial data by shifting–output data in parallel. Input data with parallel load–output data by shifting. 2.14

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2.15

2.16 (a) 4 ; (b) 9

2.17

2.18 After the count reaches N – 1 = 1001, the register loads 0000 from inputs.

2.19 (a) (b) (c) (d)

2K × 16 = 211 × 16 64K × 8 = 216 × 16 16M × 32 = 224 × 32 4G × 64 = 232 × 64

Address lines 11 16 24 32

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Data lines 16 8 32 64

2.20 (a) (b) (c) (d)

2K × 2 = 4K = 4096 bytes 64K × 1 = 64K = 216 bytes 224 × 4 = 226 bytes 232 × 8 = 235 bytes

2.21 4096 × 16 212 × 2 4 = 7 3 = 2 6 = 64 chips 128 ×8 2 ×2 2.22

2.23 12 data inputs + 2 enable inputs + 8 data outputs + 2 for power = 24 pins.

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CHAPTER 3 3.1 (101110)2 = 32 + 8 + 4 + 2 = 46 (1110101)2 = 64 + 32 + 16 + 4 + 1 = 117 (110110100)2 = 256 + 128 + 32 + 16 + 4 = 436 3.2 (12121)3 = 34 + 2 × 33 + 32 + 2 × 3 + 1 = 81 + 54 + 9 + 6 + 1 = 151 (4310)5 = 4 × 53 + 3 × 52 + 5 = 500 + 75 + 5 = 580 (50)7 = 5 × 7 = 35 (198)12 = 122 + 9 × 12 + 8 = 144 + 108 + 8 = 260 3.3 (1231)10 (673)10 (1998)10

= 1024 + 128 + 64 + 15 = 210 + 27+ 26+ 23+ 22 + 2 + 1 = (10011001111)2 = 512 + 128 + 32 + 1 = 29 + 27 + 25 + 1 = (1010100001)2 = 1024 + 512 + 256 + 128 + 64 + 8 + 4 + 2 = 210 + 29 + 28 + 27 + 26 + 23 + 22 + 21 = (11111001110)2

3.4 (7562)10 = (16612)8 (1938)10 = (792)16 (175)10 = (10101111)2 3.5 (F3A7C2)16 = (1111 0011 1010 0111 1100 0010)2 = (74723702)8 3.6 (x2 – 10x + 31)r = [(x – 5) (x – 8)]10 = x2 – (5 + 8)10 x + (40)10 x Therefore: (10)r = (13)10 r = 13 Also (31)r = 3 × 13 + 1 = (40)10 (r = 13) 3.7 (215)10 = 128 + 64 + 16 + 7 = (11010111)2 (a) 000011010111 Binary (b) 000 011 010 111 Binary coded octal 0 3 2 7 (c) 0000 1101 0111 Binary coded hexadecimal 0 D 7 (d) 0010 0001 0101 Binary coded decimal 2 1 5 3.8 (295)10 = 256 + 32 + 7 = (100100111)2 (a) 0000 0000 0000 0001 0010 0111 (b) 0000 0000 0000 0010 1001 0101 (c) 10110010 00111001 00110101 3.10 JOHN DOE - 16 -

3.11 87650123; 99019899; 09990048; 999999. 3.12 876100; 909343; 900000; 000000 3.13 01010001; 01010010; 3.14 (a)

01111110; 01111111;

5250 + 8679 1 3929

(b)

01111111; 10000000;

1753 + 1360 0 3113

11111110; 11111111;

11111111 00000000

(c)

(d)

020 + 900 0 920

1200 + 9750 1 0950

↓ = 10’s complement – 6887 – 080 3.15 (a) 11010 +10000 1 01010 (26 – 16 = 10) 3.16 + 42 = 0101010 – 42 = 1010110 (+42) 0101010 (–13) 1110011 (+29) 0011101

(b) 11010 +10011 1 01101

(c) 000100 + 010000 0 010100

(26 – 13 = 13)

–101100 (84 – 84 = 0) (4 – 48 = –44)

+13 = –13 = (– 42) (+ 13) (– 29)

0001101 1110011 1010110 0001101 1100011

3.17 01 ← last two carries → 1 0 + 70 01000110 – 70 10111010 + 80 01010000 – 80 10110000 +150 10010110 – 150 01101010 ↑ ↑ ↑ ↑ greater negative less than positive than – 128 +127

3.18 (a)

(–638) (+785) (+147)

9362 + 0785 0147

(b)

(–638) (–185) (–823)

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9362 + 9815 9177

(d) 1010100 + 0101100 1 0000000

3.19

Largest: + 0.1111 ….1 1–2-26 Smallest: + 0.1000….0 (normalized) 2 –1

+ 11111111 + 255 –11111111 –255 2–256

3.20 46.5 = 32 + 8 + 4 + 2 + 0.5 = (101110.1)2 Sign 0101110100000000 24-bit mantissa 3.21 (a) Decimal 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (b) Decimal 9 10 11 12 13 14 15 16 17 18 19 20

00000110 8-bit exponent (+6)

Gray code 11000 11001 11011 11010 11110 11111 11101 11100 10100 10101 10111 10110 10010 10011 10001 10000 Exess-3 Gray 0010 1010 0110 1010 0110 1110 0110 1111 0110 1101 0110 1100 0110 0100 0110 0101 0110 0111 0110 0110 0110 0010 0111 0010 - 18 -

(1–2–26) ×2+255

3.22 (a) (b) (c) (d)

8620 BCD XS-3 2421 Binary

1000 0110 0010 0000 1011 1001 0101 0011 1110 1100 0010 0000 10000110101100 (8192 + 256 + 128 + 32 + 8 + 4)

3.23 Decimal 0 1 2 3 4 5 6 7 8 9

BCD with even parity 00000 10001 10010 00011 10100 00101 00110 10111 11000 01001

BCD with odd parity 10000 00001 00010 10011 00100 10101 10110 00111 01000 11001

3.24 3984 = 0011 1111 1110 0100 = 1100 0000 0001 1011 = 6015 3.25 AB 00 01 10 11

Y = A⊕ B 0 1 1 0

y

z

x = y⊕ z

0

0

0

0

1

1

0

1

1

⎡ AB = 00 or 11 1 ←⎢ ⎣ CD = 01 or 10 ⎡ AB = 01 or 10 1 ←⎢ ⎣ CD = 00 or 11 0

Z = C⊕ D 0 1 1 0

CD 00 01 10 11

ABCD 0001, 0010, 1101, 1110 0100, 0111, 1000, 1011 Always odd number of 1’s

3.26 Same as in Fig. 3.3 but without the complemented circles in the outputs of the gates. P = x⊕ y⊕ z Error = x ⊕ y ⊕ z ⊕ P

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CHAPTER 4 4.1

4.2

T0T1T2T3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

S1 S0 R3 load X X 0 0 0 1 0 1 1 1 0 1 1 1 1

S1 = T2 + T3 S0 = T1 + T3 load = T0 + T1 + T2 + T3

4.3 P: R1 ← R2 P'Q: R1 ← R3

4.4 Connect the 4-line common bus to the four inputs of each register. Provide a “load” control input in each register. Provide a clock input for each register. To transfer from register C to register A: Apply S1S0 = 10 (to select C for the bus.) Enable the load input of A Apply a clock pulse.

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4.5

4.6 (a) (b) (c) 4.7 (a) (b) (c)

4 selection lines to select one of 16 registers. 16 × 1 multiplexers. 32 multiplexers, one for each bit of the registers.

Read memory word specified by the address in AR into register R2. Write content of register R3 into the memory word specified by the address in AR. Read memory word specified by the address in R5 and transfer content to R5 (destroys previous value)

4.8

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4.9

4.10

4.11

4.12 M 0 0 1 1 1

A B 0111 + 0110 1000 + 1001 1100 – 1000 0101 – 1010 0000 – 0001

Sum 1101 0001 0100 1011 1111

Cu 0 1 1 0 0

4.13

A – 1 = A + 2’s complement of 1 = A + 1111

7 + 6 = 13 8 + 9 = 16 + 1 12 – 8 = 4 5 – 10 = – 5(in 2’s comp.) 0 –1 = –1 (in 2’s comp.)

- 22 -

4.14

4.15 S 0 0 1 1

Cin 0 1 0 1

X A A A A

Y B 0 1 B

(A + B) (A + 1) (A –1) (A – B)

4.16

- 23 -

4.17

4.18 (a)

A = 11011001 ⊕ B = 10110100 A ← A ⊕ B 01101101

4.19 (a)

A = 11011001 B = 11111101 11111101

(OR)

A ← AVB

AR = 11110010 BR = 11111111(+) AR = 11110001

BR = 11111111 CR = 10111001 DR= 1110

(b)

CR = 10111001 DR = 11101010(AND) CR = 10101000

BR = 1111 1111 +1 BR = 0000 0000 AR = 1111 0001 DR = 11101010

(c)

AR = 11110001 (–1) CR = 10101000 AR = 01001001; BR = 00000000; CR = 10101000;

1010

4.20 R = 10011100 Arithmetic shift right: 11001110 Arithmetic shift left: 00111000

overflow because a negative number changed to positive.

4.21 R = 11011101 Logical shift left:

1 0111010

Circular shift right:

01011101

Logical shift right:

00101110

Circular shift left:

01011100

DR = 11101010

- 24 -

4.22 S = 1 Shift left A0 A1 A2 A3 IL 1 0010 H= 4.23 (a) (b) (c)

0010

shift left

Cannot complement and increment the same register at the same time. Cannot transfer two different values (R2 and R3) to the same register (R1) at the same time. Cannot transfer a new value into a register (PC) and increment the original value by one at the same time.

- 25 -

CHAPTER 5 5.1 256 K = 28 × 210 = 218 64 = 26 (a) Address: Register code: Indirect bit: 1 25 (b)

(c)

1

7

I

opcode

18 bits 6 bits bit 32 – 25 = 7 bits for opcode.

6 Register

18

= 32 bits

Address

Data; 32 bits; address: 18 bits.

5.2 A direct address instruction needs two references to memory: (1) Read instruction; (2) Read operand. An indirect address instruction needs three references to memory: (1) Read instruction; (2) Read effective address; (3) Read operand. 5.3 (a) (b) (c) (d)

Memory read to bus and load to IR: IR ← M[AR] TR to bus and load to PC: PC ← TR AC to bus, write to memory, and load to DR: DR ← AC, M[AR]← AC Add DR (or INPR) to AC: AC ← AC + DR

5.4

(a) (b) (c) (d) 5.5 (a)

AR ← PC IR ← M[AR] M[AR] ← TR DR ← AC AC ← DR

(1) S 2 S 1 S0 010 (PC) 111 (M) 110 (TR) 100 (AC)

(2) Load(LD) AR IR ― DR and AC

(3) Memory ― Read Write ―

(4) Adder ― ― ― Transfer DR to AC

IR ← M[PC] PC cannot provide address to memory. Address must be transferred to AR first AR← PC IR ← M[AR] (b) AC ← AC + TR Add operation must be done with DR. Transfer TR to DR first. DR ← TR AC ← AC + DR - 26 -

(c)

DR ← DR + AC

Result of addition is transferred to AC (not DR). To save value of AC its content must be stored temporary in DR (or TR).

AC ← DR, DR ← AC AC ← AC + DR AC ← DR, DR ← AC 5.6 (a)

(b)

(c)

(See answer to Problem 5.4(d))

0001 0000 0010 0010 ADD (024)16 ADD content of M[024] to AC

= (1024)16 ADD 024

1 011 0001 0010 0100 I STA (124)6 Store AC in M[M[124]]

= (B124)16 STA I 124

0111 0000 0010 0000 Register Increment AC

= (7020)16 INC

5.7 CLE Clear E CME Complement E 5.8

- 27 -

5.9 Initial CLA CLE CMA CME CIR CIL INC SPA SNA SZA SZE HLT

E 1 1 0 1 0 1 1 1 1 1 1 1 1

AC A937 0000 A937 56C8 A937 D49B 526F A938 A937 A937 A937 A937 A937

PC 021 022 022 022 022 022 022 022 022 023 022 022 022

AR ― 800 400 200 100 080 040 020 010 008 004 002 001

IR ― 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 7001

PC 021 022 022 022 022 083 084 022

AR ― 083 083 083 083 083 084 083

DR ― B8F2 B8F2 B8F2 ― ― ― B8F3

AC A937 A832 6229 B8F2 A937 A937 A937 A937

IR ― 0083 1083 2083 3083 4083 5083 6083

PC 7FF 7FF 800 800 800 800 800 801

AR ― 7FF 7FF A9F C35 C35 C35 C35

DR ― ― ― ― ― FFFF 0000 0000

IR ― ― EA9F EA9F EA9F EA9F EA9F EA9F

SC 0 1 2 3 4 5 6 0

5.10 Initial AND ADD LDA STA BUN BSA ISZ 5.11 Initial T0 T1 T2 T3 T4 T5 T6 5.12 (a)

Memory 9 = (1001) 1 001 I=1 ADD

ADD I 32E

3AF

932E

32E

09AC

9AC

8B9F

AC = 7EC3 - 28 -

(b) AC = 7EC3 DR = 8B9F 0A62

(ADD)

E=1 (c)

PC = 3AF + 1 = 3BO AR = 7AC DR = 8B9F AC = 0A62

IR = 932E E=1 I=1 SC = 0000

5.13 XOR

D0T4 D0T5

: :

DR ← M[AR] AC ← AC ⊕ DR, SC ← 0

ADM

D1T4 D1T5 D1T6

: : :

DR ← M[AR] DR ← AC, AC ← AC + DR M[AR] ← AC, AC ← DR, SC ← 0

SUB

D2T4 D2T5 D2T6 D2T7 D2T8

: : : : :

DR DR AC AC AC

XCH

D3T4 D3T5

: :

DR ← M[AR] M[AR] ← AC, AC ← DR, SC ← 0

SEQ

D4T4 D4T5 D4T6

: : :

DR ← M[AR] TR ← AC, AC ← AC ⊕ DR If (AC = 0) then (PC ← PC + 1), AC ← TR, SC ← 0

BPA

D5T4

:

If (AC = 0 ∧ AC (15) = 0) then (PC ← AR), SC ← 0

← M[AR] ← AC, AC ← DR ← AC ← AC + 1 ← AC +DR, SC ← 0

5.14 Converts the ISZ instruction from a memory-reference instruction to a registerreference instruction. The new instruction ICSZ can be executed at time T3 instead of time T6, a saving of 3 clock cycles.

- 29 -

5.15

Modify fig. 5.9.

5.16 (a)

(b)

- 30 -

(c)

T0:

IR ← M(PC), PC ← PC + 1 T1:

AR(0–7) ← M[PC], PC ← PC + 1

T2:

AR(8–15) ← M[PC], PC ← PC +1

T3:

DR ← M [AR]

5.17

1. 2. 3. 4. 5. 6. 5.18 (a) (b)

Read 40-bit double instruction from memory to IR and then increment PC. Decode opcode 1. Execute instruction 1 using address 1. Decode opcode 2. Execute instruction 2 using address 2. Go back to step 1.

BUN 2300 ION BUN 0 I

(Branch indirect with address 0)

5.19

- 31 -

5.20 JF = xT3 + Zt2 + wT5G KF = yT1 + zT2 + wT5G'

5.21 From Table 5.6: (ZDR = 1 if DR = 0 ; ZAC = 1, if AC = 0 ) INR (PC) = R'T1 + RT7 + D6T6 ZDR + PB9 (FGI) + PB8 (FGO) + rB4 + (AC15)' + rB3 (AC15) + rB2 ZAC + rB1E' LD (PC) = D4T4 + D5T5 CLR(PC) = RT1 The logic diagram is similar to the one in Fig. 5.16.

5.22 Write = D3T4 + D5T4 + D6T6 + RT1

(M[AR] ← xx)

5.23 (T0 + T1 + T2)' (IEN) (FGI + FGO) RT2

: :

R ←1 R ←0

5.24 X2 places PC onto the bus. From Table 5.6: R’T0: AR ← PC RT0: TR ← PC D5T4: M[AR] ← PC X2 = R’T0 + RT0 + D5 T4 = (R’ + R) T0 + D5T4 = T0 + D5T4

- 32 -

5.25 From Table 5.6: CLR (SC) = RT2 + D7T3 (I’+I) + (D0 + D1 + D2 + D5 ) T5 + (D3 + D4) T4 + D6T6

- 33 -

CHAPTER 6 6.1 010 011 012 013 014 015 016 017

CLA ADD 016 BUN 014 HLT AND 017 BUN 013 C1A5 93C6 (C1A5)16 (93C6)16

AC 0000 C...