Module-1 8085 Microprocessors & Architecture Module I 8085 Microprocessors & Architecture PDF

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Module-1 8085 Microprocessors & Architecture Module I 8085 Microprocessors & Architecture Microprocessors historical, perspective, 8085 pin diagram, architecture, addressing modes, overview of 8085 instruction set, microprocessor communication and bus timings, 8085 functional block diagram. ...

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Module-1

8085 Microprocessors & Architecture

Module I

8085 Microprocessors & Architecture

Microprocessors historical, perspective, 8085 pin diagram, architecture, addressing modes, overview of 8085 instruction set, microprocessor communication and bus timings, 8085 functional block diagram.

Microprocessor: It is an IC with all the functions of a CPU however, it cannot be used stand alone since unlike a microcontroller it has no memory or peripherals. It is a multipurpose, programmable, clock-driven, registerbased electronic device that reads binary instructions from a storage device called memory, accepts binary data as input and processes data according to those instructions and provide results as output. Microprocessors can be classified based on the data bus width

❖ ❖ ❖ ❖ ❖

4-Bit Microprocessors 8-Bit Microprocessors 16-Bit Microprocessors 32-Bit Microprocessors 64-Bit Microprocessors

1.History: Microproces sor

Bata Bus

Pins

No.Of transi

16 18 40 40 40 40 68 68

2300 3500 6000

134000

1978 1979 1982 1982

132 PGA

275000

1986

168 PGA

1200000

1989

273 PGA

3.1 Million 5.5 Million 7.5

1993

Intel

4004 8008 8080 8085 8086 8088 80186 80286

4-bit 8-bit 8-bit 8-bit 16-bit 8/16 bit 16-bit 16-bit

80386

32-bit

80486

32-bit

Pentium Pentium pro Pentium II

64-bit 64-bit 64-bit

640 bytes 16KB 64KB 64KB 1MB 1MB 1MB 16MB real, 4 GB Virtual 4GB real, 64TB virtual 4GB real, 64TB virtual 4GB real l 64 GB real 64 GB real

1971

1976

29000

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam.

1995 1997 Page 1

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8085 Microprocessors & Architecture

Million Pentium II XEON Pentium III Pentium IV Dual Core Core 2 Core i7 Core i5 Core i3

64-bit

1998

64-bit 64-bit

1999 2000

64-bit

2006 2006 2008 2009 2010

6800 6809 68000 68020 68030

8-bit 8-bit 16-bit 32-bit 32-bit

64KB 64KB 16MB 4GB 4GB

68040

32-bit

4GB

z-80 z-800 z-8000

8-bit 8-bit 16-bit

64KB 500K 64KB

Motorola 40 40 64 169 PGA 169 PGA

200000

1974 1978 1979 1984

Zilog 40

It is a 2nd generation microprocessor and is the base for studying and using all the microprocessor available in the market. 2. Salient features of 8085 μp: ❖ It is an 8 bit microprocessor. ❖ It has 16(A0-A15) bit address lines (AB), hence can address up to 216 = 65536 (64K) memory locations. ❖ Data bus (DB) is a group of 8 lines D0 – D7. ❖ First 8 lines of AB & 8 lines of DBs are multiplexed AD0 – AD7. ❖ It supports 5 hardware interrupt & 8 software interrupt. ❖ A 16 bit program counter (PC) ❖ A 16 bit stack pointer (SP) ❖ Six 8-bit general purpose register arranged in pairs: BC, DE, HL. ❖ It requires a signal +5V power supply ❖ Max.clock Frequency= 3MHz and Min.clock Frequency=500kHz

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam.

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8085 Microprocessors & Architecture

System Bus Bus is a group of conducting wires which carries information, all the peripherals are connected to microprocessor through Bus. There are three different types of buses. ❖ Address bus ❖ Data Bus ❖ Control Bus

Address bus –It is a group of conducting wires which carries address only. AB is unidirectional because address flows in one direction, from μp to memory or from μp to Input/output devices. The range of Address of 8085 μp is from 0000 H to FFFF H. The μp can address 65, 536 different memory location. The Length of the AB determines the amount of memory can be handled. Actual amount of memory can be accessed is usually much less than this theoretical limit due to chipset and motherboard limitations. Data bus –It is a group of conducting wires which carries Data only. DB is bidirectional because data flow in both directions, from μp to memory or Input/Output devices and from memory or Input/Output devices to μp. It is ranging from 00 H to FF H. In write operation, the μp will put the data on the DB, where as in read operation, the memory controller will get the data from specific memory block and put it into the DB. Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam.

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The width of the DB is directly related to the largest number that the bus can carry, such as an 8 bit bus can represent 2 to the power of 8 unique values, this equates to the number 0 to 255. A 16 bit bus can carry 0 to 65535. Control bus –It is a group of conducting wires, which is used to generate timing and control signals to control all the associated peripherals, μp uses control bus to process data, that is what to do with selected memory location. Some control signals are: Memory read Memory write I/O read I/O Write Opcode fetch

If one line of control bus may be the read/write line. Low on this line indicates the read operation, if this is high, it is write operation. Control and Status Signals: ALE (Address Latch Enable) signal: It goes high during first T state of a every machine cycle and enables the lower 8-bits of the address, and for the rest of the T states of the machine cycles the lower 8-bits are data nines. IO/M’ – It is a status signal which determines whether the address is for input-output or memory. When it is high (1) the address on the address bus is for input-output devices. When it is low(0) the address on the address bus is for the memory. RD’ – It is a signal to control READ operation. When it is low the selected memory or input-output device is read. WR’ – It is a signal to control WRITE operation. When it goes low the data on the data bus is written into the selected memory or I/O location. SO, S1 – These are status signals. They distinguish the various types of operations such as halt, reading, instruction fetching or writing.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam.

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IO/M’ X X X

S1 0 X X

S0 0 X X

0 0 0 1 1 1

0 1 1 0 1 1

1 0 1 1 1 1

RD’ WR’ High impedance High impedance High impedance INTA’=1 1 0 0 1 0 1 1 0 0 1 INTA’=0

Data Bus Status Halt HOLD HLD Memory write Memory read Opcode fetch I/O write I/O read Interrupt acknowledge

READY – It senses whether a peripheral is ready to transfer data or not. If READY is high (1) the peripheral is ready. If it is low (0) the microprocessor waits till it goes high. It is useful for interfacing low speed devices. Architecture:

Fig:8085 Architecture Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam.

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(a) General Purpose Registers – The 8085 has 6 general-purpose registers to store 8-bit data; these are identified as- B, C, D, E, H, and L. They can be combined as register pairs – BC, DE, and HL, to perform 16-bit operations. These registers are used to store or copy temporary data during the execution of the program. (b) Specific Purpose Registers – Accumulator: The accumulator is an 8-bit register (can store 8-bit data) that is the part of the arithmetic and logical unit (ALU). After performing arithmetical or logical operations, the result is stored in accumulator. Accumulator is also defined as register A. Flag registers: It is a special purpose register and it is completely different from other registers. It consists of 8 bits and only 5 of them are useful. The other three are left vacant and are used in the future Intel versions. The 5 flags are set or reset (1-set and 0-reset) after an operation according to data condition of the result in the accumulator and other registers. The 5 flag registers are:

Fig: flag register Sign Flag: It is 7thbit of the flag register, which is also known as the MSB. It helps the programmer to know whether the number in the accumulator is positive or negative. After any operation if the MSB of the result is 1, it in indicates the number is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number is positive and the sign flag becomes reseti.e.0. from 00H to 7F, sign flag is 0 from 80H to FF, sign flag is 11- MSB is 1 (negative) 0- MSB is 0 (positive) Example: MVI A, 30H MVI B, 40 SUB B MVI A 40 MVI B 30 SUB B

// A=30H // B=40H // (A = A – B) A=-10H S=1 // A=40H // B=30H //(A = A – B) A=10H S=0

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam.

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Zero Flag:: 6th bit of the flag register. After any arithmetical or logical operation if the result is 0 (00)H, the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.00H zero flag is 1.from 01H to FFH zero flag is 01- zero result, 0- non-zero result. It helps in determining if two numbers are equal or not. Example: MVI A, 10

//A=10H

SUB A

//(A = A – A) A=00H and Z=1

Auxiliary Carry Flag (AC): It is 4th bit of the flag register. This flag is used in BCD number system (0-9). If after any arithmetic or logical operation B(3) generates any carry and passes on to B(4) this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0. Note –Flag register in 8085 which is not accessible by user Example: MOV A, 2B MOV B ,39 ADD B

//A=2BH //B=39H //(A = A + B) A=

, AC=11

Parity Flag: It is 2nd bit of the flag register. This flag tests for number of 1’s in the accumulator. If after any arithmetic or logical operation the result has even parity, if the accumulator holds even number of 1’s, it is set, P=1. On the other hand if the number of 1’s is odd, then it is reset, P=0, it is said to be odd parity. Example:

MVI A 05 //A=05H BCD code of 05H is 00000101, hence P=1

Carry Flag: 0th bit of the flag register. Carry is generated when performing n bit operations and the result is more than n bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0. During subtraction (A-B), if A>B it becomes reset and if (A...