MT 1 - exam PDF

Title MT 1 - exam
Author Bishal Saha
Course Finite Element Methods
Institution Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology
Pages 2
File Size 108.7 KB
File Type PDF
Total Downloads 58
Total Views 151

Summary

exam...


Description

Reg.No. VTUDEC04

Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology (Deemed to be University Estd. u/s 3 of UGC Act, 1956) School of Computing Department of Computer Science and Engineering VTU R 15

MID TERM TEST – I B.Tech. - CSE Course Category Course Code/ Title Semester

: Program Core : 1151CS118/ Microprocessor and Controller : Winter

Duration Max. Marks Date of Test

: 90 Minutes : 20 : 03-05-2021

Achievable Course Outcomes CO1 : Develop an ALP in 8086 Microprocessor using the internal organization for the given specification

K3

CO2 : Understand the bus architecture of 8086 microprocessor and other advanced processors

K2

PART A Answer all the Questions. Each question carries 1 mark 1.

Identify the appropriate instruction for each of the following:

Course Marks OutcomeLevel 1

CO1

K2

1

CO1

K2

i. Copy a data from 1002H memory location to accumulator ii. Perform 2’s compliment of A7H which is present in base register 2.

Calculate the effective address for the following register: SS: 3860H, SP: 1735H, BP: 4826H

3.

Describe the use of 8288 bus controller in maximum mode operation.

1

CO2

K2

4.

Sketch the minimum mode read cycle timing diagram of 8086 microprocessor

1

CO2

K2

5.

Differentiate Instruction Cycle, Machine cycle and T- State with neat diagram.

1

CO2

K2

PART B

6.

7.

a.

Course Level Outcome

Answer any three Questions. Each question carries 5 marks

Marks

Design a pipelined architecture of a microprocessor with 1MB memory location and shall operates on 16-bit instruction to increase the performance of execution. How does the processor compute physical address of the instruction in interface unit?

5

CO1

K3

Write a program to add a data byte located at offset 0500H in 2000H segment to another data byte available at 0600H in the same segment and store the result at 0700H in the same segment.

3

CO1

K2

Page 1 of 2

Reg.No. VTUDEC04

Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology (Deemed to be University Estd. u/s 3 of UGC Act, 1956) School of Computing Department of Computer Science and Engineering VTU R 15

8.

MID TERM TEST – I B.Tech. - CSE b. Create a table to compare features for the following advanced microprocessor: Intel 80186, 80286, 80386 and 80486 and suggest a better processor to increase the performance. Explain in detail about the use of multiple processors configuration systems that execute instructions simultaneously and communicate with Maximum/Minimum mode of 8086 and how it is designed to implement in the following multiprocessor configurations:

2

CO2

K2

5

CO2

K2

i. Coprocessor (8087) ii. Closely coupled (dedicated I/O processor: 8089) iii. Loosely coupled (Multi bus) 9.

a.

The value of the DS register is 2016H. And the BX register contains a 16 bit value which is equal to 2016H. 0008H is added to BX.ADD BX, 0008H.The register AX contains some value which needs to be stored at a location as follows: MOV [BX], AX. Calculate the address at which the value of the AX will be stored.

2

CO1

K3

b.

For an effective use of stepper motor controller, propose addressing modes that can be used all levels with all data types.

3

CO2

K2

K1-Remember K2-Understand K3-Apply K4-Analyze K5-Evaluate K6-Create

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