Programmi base in ARM Assembly a 32 bit PDF

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Collezione di esercizi con allegato codice risolutivo nel linguaggio ARM Assembly a 32 bit....

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Esercizi ARM Assembly Soluzione di problemi nel linguaggio ARM

1. Scrivere un programma assembly che, dopo aver immesso in memoria, mediante una dichiarazione nella sezione .data, quattro numeri interi n1 , n2 , n3 , n4 , inserisca nei registri r0 , r1 , r2 , r3 , r4 rispettivamente i seguenti valori: • la somma dei valori n1 , n2 , n3 , n4 ; • la media dei valori n1 , n2 , n3 , n4 (arrotondando sempre verso −∞); • (210 + 1) × n1 • il resto r della divisione di n1 per 16, inteso come n1 = (n1 16)16 + r • il segno di n1 , ossia il valore 0 se n1 positivo o il valore 1 se n1 negativo Codice risolutivo: . data n : .word −3 3 , 2 0 , 3 0 , 40 . t ex t ld r r 5 , =n @ r 0 : somma d e i v a l o r i n ld r r 0 , [ r 5 ] ld r r 6 , [ r 5 , #4 ] add r 0 , r 0 , r 6 ld r r 6 , [ r 5 , #8 ] add r 0 , r 0 , r 6 ld r r 6 , [ r 5 , #12 ] add r 0 , r 0 , r 6 @ r 1 : media d e i v a l o r i n mov r 1 , r 0 , l s r #2 @ r 2 : [ ( 2ˆ 10)+1 ] ∗ n1 ld r r 7 , [ r 5 ] mov r 6 , #1 mov r 4 , r 6 , l s l #10 add r 4 , r 4 , #1 mul r 2 , r 7 , r4

@ 2ˆ 10

@ r 3 : r e s t o d i n1/ 16 ld r r 3 , [ r 5 ] and r 3 , r 3 , #15

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@ r 4 : s eg no d i n1 ld r r 3 , [ r 5 ] mov r , 4 r 3 , l s r #31 swi 0x 11 2. Dato il seguente programma assembly ARM: . t ex t mov add ld r str

r0, r0, r1, r1,

#0x 1000 r 0 , #0x 10 [ r0 ] [ r 0 , #8 ]

mov r 0 , #0 mov r 0 , #1 mov r 0 , #2 swi 0x 11 .end determinare e motivare il valore in r0 al termine dell’esecuzione. Codice con spiegazione: . t ex t @ sp iegazione @ 0x 1000 : prima l o c a z i o n e d i memoria i n c u i sono @ s a l v a t e l e i s t r u z i o n i d e l programma mov r 0 , #0x 1000 add r 0 , r 0 , #0x 10 ld r r 1 , [ r 0 ] @ s a l v a n e l l a l o c a z i o n e 0x1018 i l c o n te n ut o d i r1 @ r 1 c o n t i e n e a l momento l ’ i s t r u z i o n e a l l a l o c a z i o n e 0x1010 @ r i s u l t a t o : l ’ i s t r u z i o n e a l 0x1018 s c a m b i ata con q u e l l a @ 0x1010 s t r r 1 , [ r 0 , #8 ] mov r 0 , #0 @= r3 addlt r 2 , r 2 , #1 bl t l o g @ else subne r 2 , r 2 , #1 mov r 0 , r 2 mov p c , l r 9. Scrivere del codice assembly ARM che, nella sezione .data, definisca un numero positivo n e un vettore v contenente esattamente n numeri interi. Scrivere una procedura che, dato indirizzo e lunghezza di tale vettore nei registri r0 e r1 , azzeri tutti gli elementi del vettore aventi valore pari. Codice: . data v : .word 1 0 , 5 , 3 , 1 l : .word 4 . t ex t ld r r 0 , =v ld r r 1 , =l ld r r 1 , [ r 1 ] mov r 2 , #0 mov r 5 , #0 @ r0 : i n d i r i z z o v e t to r e @ r1 : lunghezza v etto re @ r2 : contatore bl a z z e r a p a r i swi 0x 11 @ r3 : valore corrente @ r4 : p ari o disp a ri? @ r5 : 0 azzerapari : ld r r 3 , [ r 0 , r 2 , l s l #2 ] and r 4 , r 3 , #1 cmp r 4 , #0 streq r 5 , [ r 0 , r 2 , l s l #2 ] add cmp bne mov

r 2 , r 2 , #1 r 2 , r1 azzerapari pc, l r

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ARM assembly language reference card imm12 branch to imm12 words away copy argument (S = set flags) Bcd MOVcdS reg, arg MVNcdS reg, arg copy bitwise NOT of argumentBLcd imm12 copy PC to LR, then branch ANDcdS reg, reg, arg bitwise AND BXcd reg copy reg to PC ORRcdS reg, reg, arg bitwise OR SWIcd imm24 software interrupt EORcdS reg, reg, arg bitwise exclusive-OR LDRcdB reg, mem loads word/byte from memory BICcdS reg, rega , argb bitwise rega AND (NOT argb ) STRcdB reg, mem stores word/byte to memory ADDcdS reg, reg, arg add LDMcdum reg!, mreg loads into multiple registers SUBcdS reg, reg, arg subtract STMcdum reg!, mreg stores multiple registers RSBcdS reg, reg, arg subtract reversed arguments SWPcdB regd , regm , [regn ] copies regm to memory at regn , ADCcdS reg, reg, arg add with carry flag old value at address regn to regd SBCcdS reg, reg, arg subtract with carry flag RSCcdS reg, reg, arg reverse subtract with carry flag CMPcd reg, arg update flags based on subtraction CMNcd reg, arg update flags based on addition TSTcd reg, arg update flags based on bitwise AND TEQcd reg, arg update flags based on bitwise exclusive-OR MULcdS regd , rega , regb multiply rega and regb , places lower 32 bits into regd MLAcdS regd , rega , regb , regc places lower 32 bits of rega · regb + regc into regd UMULLcdS regℓ , regu , rega , regb multiply rega and regb , place 64-bit unsigned result into {regu , regℓ } UMLALcdS regℓ , regu , rega , regb place unsigned rega · regb + {regu , regℓ } into {regu , regℓ } SMULLcdS regℓ , regu , rega , regb multiply rega and regb , place 64-bit signed result into {regu , regℓ } SMLALcdS regℓ , regu , rega , regb place signed rega · regb + {regu , regℓ } into {regu , regℓ } reg: register R0 to R15 SP LR PC um: IA IB DA DB

register according to number register 13 register 14 register 15

update mode increment, starting from reg increment, starting from reg + 4 decrement, starting from reg decrement, starting from reg − 4

cd: condition code AL or omitted always EQ equal (zero) NE nonequal (nonzero) CS carry set (same as HS) CC carry clear (same as LO) MI minus PL positive or zero VS overflow set VC overflow clear HS unsigned higher or same LO unsigned lower HI unsigned higher LS unsigned lower or same GE signed greater than or equal LT signed less than GT signed greater than LE signed less than or equal

arg: right-hand argument #imm8∗ immediate (rotated into 8 bits) reg register reg, shift register shifted by distance mem: memory address [reg, #±imm12] reg offset by constant [reg, ±reg] reg offset by variable bytes [rega , ±regb , shift] rega offset by shifted variable regb † [reg, #±imm12]! update reg by constant, then access memory [reg, ±reg]! update reg by variable bytes, access memory [reg, ±reg, shift]! update reg by shifted variable† , access memory [reg], #±imm12 access address reg, then update reg by offset [reg], ±reg access address reg, then update reg by variable [reg], ±reg, shift access address reg, update reg by shifted variable† † shift distance must be by constant shift: shift register value LSL #imm5 shift left 0 to 31 LSR #imm5 logical shift right 1 to 32 ASR #imm5 arithmetic shift right 1 to 32 ROR #imm5 rotate right 1 to 31 RRX rotate carry bit into top bit LSL reg shift left by register LSR reg logical shift right by register ASR reg arithmetic shift right by register ROR reg rotate right by register...