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ECE332 LOGIC CIRCUIT LAB

Three Floor Elevator Lab 9 .

Objective In this lab experiment main purpose is to design the finite state machine for the three floor elevator system. For this circuit will be design through the proper designing like state diagram, state table, transition table, K-Maps and reduced Boolean equations. Than circuit will be tested in the QuartusII Prime software and simulation will test.

Experiment List  74LS154 Decoder IC  D Flip Flop  2-input NAND Gate  3-input NAND Gate  4-input NAND Gate  6-input NAND Gate

Procedure In this lab three floor elevator controller is designed through the finite state machine. As this elevator have two buttons that tells the elevator will go up or down. ‘R’ & ‘S’ button define the next floor of the elevator. Further there are LEDs that define the current state of the elevator. First we draw the state diagram for the elevator and then by using the state diagram state table and transition table is filled. Than by using the 4 to 16 decoder input values of flip flop and outputs functions are define. Then we created the project in the Quartus Prime software and created the schematic diagram file in which 74LS154 decoder IC is used with the D flip flops and NAND gates. After compile the project successfully a simulation waveform is created that test the working of the finite state machine. Design of the circuit is below:-

Design State Diagram

State Table State F1 F2 F3

RS 01 F2 F2 F2

00 F1 F1 F2

10 F2 F3 F3

Transition Table D R 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Present State C B Q1 Q2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

A S 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Boolean Equations D1 = (O10 O11 O12 O13)’ D2 = (O1 O3 O4 O5 O8 O9)’ Up = (O1 O8 O9 O10 O11)’ Dn = (O2 O4 O5)’ A = (O0 O1 O8 O9)’ B = (O2 O3 O10 O11)’ C = (O4 O5 O12 O13)’

Decoder Output O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

Next State Q1+ 0 0 0 0 0 0 X X 0 0 1 1 1 1 X X

Q2+ 0 1 0 1 1 1 X X 1 1 0 0 0 0 X X

Outputs Up 0 1 0 0 0 0 X X 1 1 1 1 0 0 X X

Dn 0 0 1 0 1 1 X X 0 0 0 0 0 0 X X

A 1 1 0 0 0 0 X X 1 1 0 0 0 0 X X

B 0 0 1 1 0 0 X X 0 0 1 1 0 0 X X

C 0 0 0 0 1 1 X X 0 0 0 0 1 1 X X

Circuit Schematic

Result

When R is 1 and S is 0 than elevator goes upward and when R is 0 and S is 1 than elevator goes downward and when both are 0 than elevator remain at the same floor. ABC shows the floor LED. UpDn signal shows that motor goes upward or downward. State shows the state that define in the state diagram. When reset is 0 than state set to initial state and elevator runs normally when reset is 1. Elevator transition occur at the positive edge of the clock signal.

Conclusion By doing this experiment we are able to design the FSM by using the decoder, flip flops and some logic gates. Also we knows that how to construct the circuit in the QuartusII prime software and how to check the simulation result by using the waveform. Now we can design the sequential circuits easily by using the proper designing method....