Two-transistor step-down DC/DC converters with fault-tolerant capability PDF

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Two-Transistor Step-Down DC/DC Converters with Fault-Tolerant Capability Dylan Dah-Chuan Lu, and John Long Soon Dries Verstraete School of Electrical and Information Engineering School of Aerospace, Mechanical The University of Sydney, NSW 2006, Australia and Mechatronic Engineering Email: dylan.lu@...

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Two-Transistor Step-Down DC/DC Converters with Fault-Tolerant Capability Dylan Dah-Chuan Lu, and John Long Soon

Dries Verstraete

School of Electrical and Information Engineering The University of Sydney, NSW 2006, Australia Email: [email protected], [email protected]

School of Aerospace, Mechanical and Mechatronic Engineering The University of Sydney, NSW 2006, Australia Email: [email protected]

Abstract—This paper presents a family of two-transistor stepdown dc/dc converters with fault-tolerant capability which is derived through graph theoretic approach. The fault-tolerant property deals with open-circuit fault of one of the power transistors in a two-transistor dc/dc converter structure. Under normal operation, either one of the two transistors can be used to control the power flow and the other transistor is idle. When the fault occurs, the other transistor will be activated to provide an alternate current path to continue converter operation and maintain output regulation. Derivation procedure and some experimental results are reported. Index Terms—dc/dc converter, fault-tolerant, graphs, opencircuit fault

I. I NTRODUCTION Reliable electric power supply, which is increasingly managed by switching power converters, is critical to sustain all our power-related activities. The power supply connects various power sources such as renewable energies and battery to the grid and applications covering commercial, industrial, and residential customers. These activities will come to a halt when the power supply fails. One industry report presents a study of 350 onshore wind turbines worldwide and shows that the frequency converter (one type of switching power converter) contributes to 13% of the total system failure rate [1]. The same problem is also identified in variable speed drives [2], solid-state lighting (LED) [3], telecommunication/server power [4], automobiles and mobile devices [5]. Many switching power converters stop operation when an internal circuit fault occurs. As identified in [6], [7], the weakest link in a photovoltaic (PV) inverter is the power transistor (MOSFET and IGBT). Solutions from different directions for reducing the chances of power transistor failure have been devised, such as thermal management, advanced semiconductor packaging, component selection, printed circuit board design and prognostics mechanism [5], [8]. However, when a power transistor fault does happen, a fault-tolerance mechanism must be in place and activated so that the powerrelated activities can continue fully or to an acceptable range. Adding redundancy to power supply improves its reliability. N+M and 2N redundancy concepts have been proposed [9] and adopted by the industry [10], where N is the minimum number of power supply in parallel for normal operating condition and M is the number of additional power supply to create

the required levels of redundancy. This is an ideal solution for power supply system with multiple modules sharing the total output power. However it may not be practical and costeffective if space or weight is of primary concern such as in mobile devices or each power supply module share significant portion of the total system cost. Fault-tolerant circuits can be built into the switching power converters. This reduces the overall power supply size and cost while providing sufficient levels of redundancy. One example is the H-bridge multilevel inverter with fault-tolerant capability [11]–[14] due to the fact that there are more than one current paths to provide the same output voltage level. If a power transistor is short-circuited or open-circuited, the faulty transistor will be isolated and another current path will be routed to continue converter operation. This solution is effective if there are many power transistors and the converter is of multilevel structure. Another example is a three-level dc/dc converter which consists of two boost converters (twolevel by itself) connected in series for PV application [15]. When the power transistor in one of the boost converters experiences an open-circuit fault, a TRIAC switch is turned on to create an alternate current path. Even though some topologies are reported on two-level and multi-level converters, there is a lack of tool to systematically evaluate and characterize these solutions and generate newer and optimal solutions to cover different combinations and a wide spectrum of customized specifications. In addition, for two-level switching converters, it is difficult to have builtin fault-tolerant capability due to limited number of power transistors. This paper addresses the open-circuit fault of two-level dc/dc switching power converters. The open-circuit fault in this paper is defined as the situation where a power transistor is open-circuited due to lifting of the bonding wires which is caused by thermic cycling, gate-drive open-circuit fault or short-circuit-fault-induced transistor rapture [16]. A straightforward approach is to insert another identical transistor in parallel with the main transistor. The additional transistor works in stand-by mode until open-circuit fault of the main transistor occurs. Using a separate gate driver for this additional transistor may improve reliability further. However, caution must be taken when designing the printed circuit board

so that the connections of this additional transistor will not be open when fault occurs as the two transistors share the same terminals which connect to the rest of the power stage circuit (e.g. drain and source terminals if MOSFETs are used). To avoid the possibility of open connections affected by the faulty transistor, this paper proposes to insert the additional transistor in a different position of the power stage circuit while utilising all other devices in the circuit for power conversion. This can be achieved by integrating two different converters with similar properties into a single converter structure while keeping the two transistors separated. Graph theoretic approach is adopted [17]–[19] to synthesize converter circuits in an analytical and systematical manner. The paper focuses on synthesis of step-down dc/dc converters with faulttolerant capability.

1

2 bb

+

S1

Aa =

Vo

RL

− bb

+ b

1

S1 −

bb

0 (a) b

b

b

2

−

−

S2

S1

+

+ b

−

S2 +

a

0

b

(b) dc circuit

(c) ac circuit

Fig. 1. A buck converter (a), its dc equivalent circuit (b) and ac equivalent circuit (c).

1

Node  S1 S2  0 1 0 0  1  1 −1 −1 2

(1)

 S1 1 −1

(2)

S2  1 −1

C

L1

This paper adopts the converter synthesis approach proposed by Makimovi´c [17] and extended by Zhou [18], focusing on voltage-to-voltage converters. The synthesis first considers different ac equivalent and dc equivalent circuits (or graphs) of the basic structure of the converters to be derived and two reference directions of each switch (transistor and/or diode). For ac circuits the voltage sources and capacitors are shorted while the current sources and inductors are removed. For dc circuits the capacitors are removed while the inductors are shorted. The sources and loads are considered as external elements and the dc circuit contains only switches. As an example, the buck converter and its ac and dc equivalent circuits are shown in Fig. 1. Note that S1 and S2 operate in an alternative manner. The basic buck converter contains one inductor and one capacitor (1L-1C). Using the same ac and dc equivalent circuits, converters with same ac and dc characteristics but with high order circuits, e.g. 2L-2C, 3L3C, etc. and even different voltage conversion ratio can be derived. The next step of synthesis of other possible converter topologies is carried out through inserting inductors and capacitors at different positions of the dc and ac equivalent circuits. The dc and ac equivalent circuits (or graphs) of the buck converter are represented by the incidence matrices Ad and Aa , as shown in (1) and (2) respectively. This enables an efficient computational method to derive circuits particularly when the order of the circuits and number of switches increase. The nodes of the equivalent circuits are labelled as shown in Fig. 1(b) and (c). The nodes are reflected in the matrices.

Node a b

S2

Vin

II. R EVIEW OF S YNTHESIS OF BASIC DC/DC C ONVERTERS

Ad =

bb

L

Vin b

1′

bb

bb

L2

2′ C1

S1 S2

2

+

C2

RL

Vo −

bb

0

bb

Fig. 2. A 2L-2C buck-boost converter is formed using the dc and ac equivalent circuits of buck converter. It combines a boost converter and a buck converter in an integrated approach, i.e., devices C1 , S1 and S2 are shared. It is recognized as a three-port converter in [20].

Once the incidence matrices are formulated, the rows of Ad are compared with that of Aa to determine the location of inductors. The inductor is inserted when the two nodes under comparison show different entries other than 0. For example, the entry “1” in row 0 does not appear in row b. Node 1 is split into node 1 and node 1′ and an inductor is to be inserted between the two nodes. Each node in Ad is compared to that in Aa until the incidence matrix Ad is modified. Recall that the nodes of inductors are shorted in dc equivalent circuits. This procedure retrieves all the nodes. The final step is to add the capacitors by connecting the nodes in the modified Ad to the corresponding node in Aa . For example, suppose nodes 0 and 2 of Ad are grouped to node a of Aa , the revised incidence matrix A′d will be given by

A′d

=

Node 0 1′ 2 1 2′

 S1 S2 0 1  1 0   0 0   0 0 −1 −1



  .  

(3)

Fig. 2 shows the resultant 2L-2C converter using (3). The resultant circuit is a cascade and integrated connection of boost converter and a buck converter. The theoretical voltage

conversion ratio in continuous conduction mode is 1 Vo = ·d Vin 1−d

(4)

+

The objective of the synthesis process is to merge two partly different converters together to form new converters which have two separate transistors. All other parts are shared and the converter can operate with either transistor alone. This provides the converter with fault-tolerant capability when one of the transistors fails to operate due to open-circuit fault. The other transistor can be activated to continue converter operation and maintain output regulation. Fig. 3 shows a ZETA converter and its dc and ac equivalent circuits. Compared with the buck converter in Fig. 1, it has a different dc equivalent circuit but the same ac equivalent circuit. By superimposing the dc equivalent circuit of buck converter on that of ZETA converter, a new dc circuit is formed. Similarly, a new ac circuit is also formed. The new dc and ac equivalent circuits are shown in Fig. 4. The faulttolerant capability of the new converter can be observed from the new dc circuit. When switches S1 and S3 operate and S2 is idle, it is effectively a ZETA converter. When S2 and S3 operate and S1 is idle, it is a buck converter operation. Both circuit operations share S3 which can be a diode as it is originally used for the buck and ZETA converters. The incidence matrices Ad and Aa of the dc and ac circuits in Fig. 4 respectively are given by

1

 S1 S2 S3  0 −1 1  1 1 0  −1 0 −1 2

b

bb

(5)

bb

L2 C1 S1

+

S2

L1

Vin

C2

RL

Vo −

b

bb

(a)

bb

0 b

1

b b

+

−

S1

S2 +

− b

0

(b) dc circuit

b

2 −

−

S1

S2

+

2

S3 +

− b

−

−

−

+

+

+

S1

0

S2

S3

b

a (b) ac circuit

(a) dc circuit

Fig. 4. Equivalent circuits of a buck converter superimposing on a ZETA converter.

III. S YNTHESIS OF PWM S TEP -D OWN DC/DC C ONVERTERS WITH FAULT-T OLERANT C APABILITY

Ad =

b

−

S2

which is effectively an inverting buck-boost converter with both smooth input and output currents. This converter is reported as a three-port power conditioner for renewable generation [20].

Node 0 1 2

b

b b

S1 −

+

1

+

a

iS1

1

2

bb

bb

bb

iD

S1

+

Vin

RL

C

D

Vo −

iL

L

bb

bb

0′

0 iS2 S2

Fig. 5. Derived 1L-1C step-down dc/dc converter with fault-tolerant capability. When S1 operates it is a buck converter; when S2 operates it is a buck-boost converter. If either S1 or S2 is open-circuited, the other transistor will continue converter operation and maintain output regulation.

Aa =

Node a b



S1 S2 S3  1 1 1 . −1 −1 −1

(6)

Suppose nodes 0 and 1 of Ad are grouped into node a of Aa , the modified incidence matrix A′d is expressed as

A′d =

Node 0 1 0′ 2

S1 S2 S3 0 0 1  1 1 0   0 −1 0 −1 0 −1 



 . 

(7)

Using (7), a new 1L-1C step-down dc/dc converter with opentransistor fault-tolerant capability is derived, as shown in Fig. 5. When S1 is operational and S2 is idle, the circuit is a buck converter, as shown in Fig. 6. When S2 is operational and S1 is idle, it is a buck-boost converter, as shown in Fig. 7. Apart from the switches, all other parts, i.e. diode D, inductor L and output capacitor C, are shared. Other topologies can be derived when grouping different nodes. Fig. 8 shows another topology with two inductors and two capacitors as a result of grouping nodes 1 and 2 into node a. When S1 is switching (S2 is idle), the circuit is a buck converter. When S2 is switching (S1 is idle), it is a ZETA converter. Fig. 9 shows another variation with three inductors and three capacitors as a result of grouping nodes 0 and 1 into node b.

b

(c) ac circuit

Fig. 3. A ZETA converter (a), its dc equivalent circuit (b) and ac equivalent circuit (c).

IV. E XPERIMENTAL RESULTS To verify the proposed converter synthesis concept, the 1L1C step-down converter in Fig. 5 was built and tested. The

iS1 bb

bb

bb

S1

C2

+

Vin

RL

C

D

bb

bb

Vo

bb

bb

L3

L1

−

S2

L

iL bb

+

bb

Vin

S1

D

C3

RL

Vo

C1 − S2

(a) Buck mode and S1 is ON

L2 bb

iS1 bb

bb

Vin

bb

bb

bb

iD

S1

bb

Fig. 9. Derived 3L-3C step-down dc/dc converter with fault-tolerant capability.

+ RL

C

D

Vo −

L

iL bb

bb

S2

(b) Buck mode and S1 is OFF Fig. 6. Equivalent circuits of Fig. 5 when the converter operates in buck mode and continuous conduction mode. bb

bb

bb

S1

+

Vin

RL

C

D

Vo −

L

iL bb

bb

iS2 S2

(a) Buck-boost mode and S2 is ON bb

bb

bb

Fig. 10. Experimental results of the 1L-1C converter in buck mode (S1 operates only). Scales: PWM (5V/div), high-side (20V/div), inductor current iL (200mA/V), and output voltage Vo (7.5V/div). Time base: 10µs/div.

iD

S1

+

Vin

RL

C

D

Vo −

L

iL bb

bb

S2

(b) Buck-boost mode and S2 is OFF Fig. 7. Equivalent circuits of Fig. 5 when the converter operates in buck-boost mode and continuous conduction mode.

bb

bb

bb

L1 S1 S2 + bb

Vin

C2

bb

RL

C1

Vo −

L2

D

bb

bb

bb

Fig. 8. Derived 2L-2C step-down dc/dc converter with fault-tolerant capability. This circuit is same as that reported in [21] which is applied for power factor correction.

Fig. 11. Experimental results of the 1L-1C converter in buck-boost mode (S2 operates only). Scales: PWM (5V/div), high-side (20V/div), inductor current iL (200mA/V), and output voltage Vo (7.5V/div). Time base: 10µs/div.

inductace L and output capacitance C are used 80µH and 2200µF respectively. The input voltage is at 12V and output voltage is at 5V/2.5A. The converter works in continuous conduction mode and at 100kHz. Fig. 10 shows the experimental results of the converter in buck mode while Fig. 11 shows the buck-boost mode. The converter was able to maintain at around 5V for both modes. Note that the duty cycle has to change as the voltage conversion ratios in buck mode and in buck-boost mode are different. V. C ONCLUSIONS This paper presented a systematic approach to deriving two-level non-isolated dc/dc step-down converters with faulttolerant capability. The fault tolerance is referred to the opencircuit fault of the power transistor. To enable continuous converter operation, the objective of the converter synthesis process is to combine two slightly different converters so that the converter derived share all devices except for two separate transistors. The converter is able to operate with just one transistor. The other transistor is inactive until an open-circuit fault of the active transistor occurs. This approach minimises the additional component count to implement the fault-tolerant feature. A graph theoretical approach is adopted in this paper to synthesize the converters. Experimental results of a selected converter showed that it is able to maintain output regulation with either transistor in action. This paper mainly focused on synthesis of converters instead of fault detection algorithms and control. Some of these techniques have been reported in [11]–[14]. R EFERENCES [1] M. Wilkinson and B. Hendriks, “Report on wind turbine reliability profiles. work package WP1 - field data reliability analysis,” Reliawind, Tech. Rep., 2010. [2] F. Fuchs, “Some diagnosis methods for voltage source inverters in variable speed drives with induction machines - a survey,” in The 29th Annual Conference of the IEEE Industrial Electronics Society (IECON), vol. 2, Nov 2003, pp. 1...