Unit 2 - Introduction to Intel s 8086/88: Register model Bus interface Unit Execution PDF

Preview

Summary

Introduction to Intel s 8086/88: Register model Bus interface Unit Execution unit
Control Unit: hardwired and microprogrammed control. Memory organization: the Basic memory cell
RAM, ROM, and DRAM
associative, cache and virtual memory organizations...

Description

UNIT II INTRODUCTION TO INTEL’S 8086/88 Register model: General Registers: The CPU contains a small set of internal registers as temporary storage for data. The register set can be seen as a small memory. The CU ensures that the data from the correct internal registers is presented to the ALU and that the data from the CPU is placed back in the correct register. Some registers have specific functions and this is particularly true of Intel Architecture processors. It is common to use one register to hold the output of ALU operations and this register is referred to as the accumulator. The status or flags register contains individual bits to store condition information e.g. flag if the last arithmetic result was positive or negative. The Program Counter register The Program Counter register is used to point to the next instruction to be executed. In the 8086 processor the term Instruction Pointer is used in place of Program Counter. We will use the terms interchangeably. The Stack Pointer Register The stack is part of the main memory where program information can be conveniently stored by a simple push operation and restored by a simple pop operation. The stack area in main memory is defined under program control and the stack pointer register keeps track of the next memory location available on the stack. The stack is operated as a FILO (first in last out) type of buffer. Data register Address register Status register Index register Segment register

8, 16, 32 bit general register structure

Segment Registers

32 bit Base & Index Registers

32 bit EU

Registers for a variety of purposes such as holding the address of instructions and data, storing the result of an operation, signaling the result of a logic operation, or indicating the status of the program or the μp itself. Some registers may be accessible to programmers, while others are reserved for us by the μp itself. Registers store binary values such as 1 or 0 as electrical voltages of say 5 volts or 0 volts. They consist of several integrated transistors which are configured as a flip-flop circuits each of which can be switched into a 1 or 0 state. They remain in that state until changed under control of the μp or until the power is removed from the processor. Each register has a specific name and is addressable, some, however, are dedicated to specific tasks while the majority are general purpose. The width of a register depends on the type of μp, e.g., an 16, 32 or 64 bit microprocessor. In order to provide backward compatibility, registers may be sub-divided. For example, the Pentium processor is a 32 bit CPU, and its registers are 32 bits wide. Some of these are sub-divided and named as 8 and 16 bit registers in order to run 8 and 16 bit applications designed for earlier x86 microprocessors. Instruction Register : When the Bus Interface Unit receives an instruction it transfers it to the Instruction Register for temporary storage. In Pentium processors the Bus Interface Unit transfers instructions to the L1 I-Cache, there is no instruction register as such. Stack Pointer : A stack is a small area of reserved memory used to store the data in the μ p’s registers when: (1) system calls are made by a process to operating system routines; (2) when hardware interrupts generated by input/output (I/O) transactions on peripheral devices; (3) when a process initiates an I/O transfer; (3) when a process rescheduling event occurs on foot of a hardware timer interrupt. This transfer of register contents is called a context switch. The stack pointer is the register which holds the address of the most recent stack entry. Hence, when a system call is made by a process (to say print a document) and its context is stored on the stack, the called system routine uses the stack pointer to reload the register contents when it is finished printing. Thus the process can continue where it left off. General Registers :

The data registers can be addressed by their upper or lower halves. Each data register can be used interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always accessed as 16-bit values. The μp can use data registers without constraint in most arithmetic and logic operations. Arithmetic and logic operations can also use the pointer and index registers. Some instructions use certain registers implicitly (see Table 1), allowing compact encoding. Table 1. Implicit Use of General Registers Register AX AL AH BX CX CL DX SP SI DI

Operations Word Multiply, Word Divide, Word I/O Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal Arithmetic Byte Multiply, Byte Divide Translate String Operations, Loops Variable Shift and Rotate Word Multiply, Word Divide, Indirect I/O Stack Operations String Operations String Operations

Bus interface Unit: Facilities communication between the EU and memory or I/O circuits. It is responsible for transmitting address, data, and control signals on the buses. Its registers are named CS, DS, ES, SS, IP; they hold addresses of memory locations. The IP contains the address of next instruction to be executed by the EU. The Main Units in the BIU are: Instruction Queue Address calculation unit Segment registers Instruction pointers

Execution unit: (EU) is used mainly to execute instructions. It contains a circuit called the arithmetic and logic unit (ALU). The ALU performs arithmetic ( + , - , * , / ) and logic (AND, OR, NOT) operations. The data for operations are stored in circuit called Registers. A register is like a memory location except that we normally refer to it by a name rather than address. The EU has eight registers for storing data; their names are AX, BX, CX, DX, SI, DI, BP, SP and FLAGS register.

Control Unit: hardwired and micro programmed control: The control unit coordinates and manages μp activities, in particular the execution of instructions by the arithmetic and logic unit (ALU). In Pentium processors its role is complex, as microcode from decoded instructions are pipelined for execution by two ALUs. Main Functions are: Fetching Instructions Analyzing OPCAODE Generating control signals for performing various micro-operations Hardwired and micro programmed control: Instead of executing a series of micro coded instructions the Control Unit and Execution Unit use logic gates to implement each operation. The smaller instruction set means that the codes to be decoded and implemented are smaller so that more effort can be put into this area.

MEMORY ORGANIZATION Basic memory cell –RAM, ROM and DRAM: RAM: Random access memory (usually known by its acronym, RAM) is a type of computer data storage. It takes the form of integrated circuits that allow the stored data to be accessed in any order, i.e. at random. The word random thus refers to the fact that any piece of data can be returned in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.

This contrasts with storage mechanisms such as tapes, magnetic discs and optical discs, which rely on the physical movement of the recording medium or a reading head. In these devices, the movement takes longer than the data transfer, and the retrieval time varies depending on the physical location of the next item. The word RAM is mostly associated with volatile types of memory, where the information is lost when power is switched off. However, many other types of memory are RAM as well (i.e. Random Access Memory), including most types of ROM and a kind of flash memory called NOR-Flash. ROM: As the name implies, this type of memory is readable only. The memory will hold its contents in power off state, i.e. it is non-volatile. The memory cells are physically programmed by coating with a metal mask during manufacture. The data set and/or program will therefore have been produced before the chip was manufactured. This technology is only economically reasonable for large quantities of identical chips. Due to rapidly changing memory technology, these devices are becoming much less popular. A typical application is the firmware inside a pocket calculator.  Programmable ROM (PROM) This type of memory is programmable only once. The programming is realised by blowing the (fusible) links inside addressed cells using specialised equipment. The technology is usually bipolar and because of the relative high power dissipation and low bit density belongs to history now. A typical application is the preloading of other programmable devices.  Erasable Programmable ROM (EPROM) This type of memory can be programmed and erased multiple times. Programming is carried out using specialised programming equipment. The memory may be erased by exposing it to UV-B radiation. Therefore this type of chip has a package with a quartz window to allow erasure of the chip. An EPROM is almost always a MOS device giving it superior bit density and low power operation. Programming is carried out by raising the supply voltage and injecting electrons in the cell free floating gate through the hot-electron mechanism. Programmed data will remain for 10 years minimum, and over 100 years typically. As the programming operation is performed under high voltage it wears out the chip and only a limited number of program-erase cycles can be done, typically a hundred to thousand. The number of read cycles is unlimited, classifying it as a read-only device.

EPROM’s allow program alteration after a product has been designed and are a natural choice for systems needing on-board fixed (or at least nonvolatile) program memory, which may be modified easily in production. A typical application is the program memory for a micro-controller operated washing machine or a computer bios.  Electrically Erasable Programmable ROM (EEPROM) This memory technology is both electrically erasable and programmable. The technology is always MOS type, but density is less than that of EPROM’s since it has higher technological complexity. Programming is done by either hot electron injection or Fowler-Nordheim tunnelling into a cell's floating gate. Cell erasure is achieved by removing the charge from the floating gate using tunnelling again. Both programming and erasure are done under a higher supply voltage, which is usually generated inside the device. Erasure may be done bit by bit, but is done byte-wise in most devices for practical reasons. The number of program/erase cycles a cell can have ranges from ten thousand to millions of times, dependent on the actual technology used and the manufacturer. Since programming and erasure is limited and slow (typically 5ms) these devices are still categorized as read-only devices, since the number of read cycles is unlimited. The data retention time is ten to over hundred years, and data is non-volatile. Typical applications are the storage of telephone numbers in the GSM telephone of a fax machine, or the storage of settings on a digital monitor or a TV-set, etc. The ATmega8 micro-controller has 512 bytes of EEPROM data memory (with a life expectancy of 100,000 programming cycles).  Flash ROM This type of memory is basically identical to EEPROM technology except that the whole memory, or a sector of the memory is erased at one time. The advantage is that a higher density is achieved and therefore the price per bit is cheaper. Typical applications are solid-state disks and firmware memory. Flash ROM’s have an advantage over EPROM’s that they can be reprogrammed while residing on board. A Flash ROM could thus be reprogrammed over a modem line without touching the hardware. The ATmega8 micro-controller has 8192 bytes of Flash ROM organised as 4096 sixteen bit instruction words. DRAM: DRAM memory is different from SRAM in the sense that the cells are not bi-stable elements but just addressed capacitors holding a charge which represents

the state of the cell. As this charge leaks away over time the cell needs to be read and re-programmed regularly. Typically this must be done each 4-100ms for the whole array. Since the state of the cell is a mere analogue voltage the technology is called dynamic. The technology has several disadvantages. Since the data is a charge, which may be disturbed by internal or external events, the soft error rate is higher than with other types of memory. Also, the complexity of the circuits controlling the memory is much higher since the address bus is generally multiplexed and the cells must be refreshed regularly. During refresh the memory may not be available for data, dependent on the refresh scheme used. Finally, dynamic RAM is slower than static RAM. Its only advantage over static ram is cost of manufacture. Dynamic ram is a four times cheaper per bit than static RAM, explaining its wide use in computer applications where large quantities of memory are required for data or program memory. Today, DRAM's come in different technologies, which are all designed to overcome one of the biggest drawbacks of DRAM’s speed.

Associative, cache and virtual memory organizations: Associative memory: "Content addressable" memory Locations containing data have a "valid" bit set Provide data to locate in memory (+ a mask to indicate significant part) Memory sets "match" bits for matching locations One of the matches appears in the output register Much more complex than typical RAM Associative cache: Store tuples: for cached RAM locations Match on address part to retrieve cached data Optimization: store a whole block/line of RAM in each location  Retrieve multiple RAM locations for each cache hit  Take advantage of locality of reference Direct Mapped Cache: Build it out of conventional RAM Break address into 3 fields:  high order "match" or "tag" bits  mid-order bits - width matches address width of cache  low-order bits - select individual words within a cache block Store this in each location in the cache  the "match" or tag bits for this cache entry  block of data copied from corresponding RAM location  "valid" bit if this cache location is valid Each address reference goes to a specific address in the cache, based on the address' mid-order bits

 If the address' high order bits match the cache entry's tag bits,  AND the "valid" bit is true  THEN retrieve the data from the cache Does this really work?  Takes advantage of locality of reference  You get "cache thrashing" if the program is using two distant pieces of RAM simultaneously that overlap mid-order bits Set Associative cache: Think of a direct mapped cache whose locations can store match and data for 2 or more locations Each location contains 2 or more of these "cache entries"  "match" or "tag" bits  valid bit  counter - incremented each time the entry is used "N way set associative cache" has N cache entries for each location in the RAM. Cache replacement policies: FIFO  starts at top, goes to bottom, replaces oldest first  generally good performance, needs a pointer LRU - least recently used  needs extra memory to track use of each location  Not generally used with associative cache  Frequently used with set-associative cache Random - picks spot at random  produces good performance, similar to FIFO Cache writing policies: Write-through = always write to RAM immediately when data is modified Write-back = write to RAM eventually, but not immediately Reaction to Write-Miss (writing to location not already in the cache)  Write-Allocate = always set aside space in the cache - often used with writeback  Write-No-Allocate = don't allocate cache space - often used with writethrough Virtual Memory: Segmentation - origin of virtual memory Paging - current popular approach to virtual memory Multilevel page tables Segmentation + paging...