Unit9 - 8051 - Lecture notes 9 PDF

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EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS(Credit - 4)Unit Nine: 8051 MicrocontrollerJabir Hussain([email protected])School of Electronics EngineeringKIIT UniversityNovember 19, 2017Introduction1 IntroductionA microcontroller can be termed as acomputer-on-chipin contrast to a microprocessor which i...

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EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS (Credit - 4)

Unit Nine: 8051 Microcontroller

Jabir Hussain ([email protected]) School of Electronics Engineering KIIT University

November 19, 2017

Introduction

1

Introduction

A microcontroller can be termed as a computer-on-chip in contrast to a microprocessor which is only a processor-on-chip. A microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, interrupt logic, and timers all on a single chip. In other words, all the components which make up a microprocessor-based system are embedded together on one chip. In 1981, Intel Corporation started the MCS-51 family of microcontrollers with the introduction of 8051 microcontroller. It has the following features. • 4KB of on-chip ROM. • 256 bytes of on-chip RAM, where 128 bytes are user accessible RAM and the other 128 bytes are reserved for Special Function Registers (SFRs). • 8-bit processor, meaning its ALU, most of the registers, and data bus is of 8 bits. • 16-bit address bus capable of accessing 64 KB each of external RAM and ROM. • Four 8-bit I/O ports. • Five interrupts. • Two 16-bit counter/timers. • A serial interface. • Oscillator and clock circuits operating with crystal frequency ranging from 12 to 40 MHZ giving an effective cycle rate of 1 to 3.33 MHz.

1

Architecture

2

Architecture

The basic internal block diagram of an 8051 microcontroller is shown below. External Interrupts

SFR Internal Interrupts Interrupt Control

128 bytes On-chip ROM

User-accessible

128 bytes 4KB

Timer 1

On-chip RAM

Timer 0

4 8-bit I/O Ports

Serial Interface

8-bit CPU

Oscillator Circuit

Bus Control

P0

P2

P1

P3

used to interface 64 KB external RAM and/or ROM

2

TXD

RXD

Counter Inputs

Pins and Signals

3 3.1

Pins and Signals Pin Diagram

The 8051 microcontroller is packaged in a 40-pin DIP, requires a 5V power supply and operates with 12-40 MHz crystal frequency. Its pinout is shown below.

P1.0

1

40

VCC

P1.1

2

39

P0.0

(AD0 )

P1.2

3

38

P0.1

(AD1 )

P1.3

4

37

P0.2

(AD2 )

P1.4

5

36

P0.3

(AD3 )

P1.5

6

35

P0.4

(AD4 )

P1.6

7

34

P0.5

(AD5 )

P1.7

8

33

P0.6

(AD6 )

RST

9

32

P0.7

(AD7 )

(RXD)

P3.0

10

8051

31

EA/VPP

(TXD)

P3.1

11

µC

30

ALE/PROG

(INT0)

P3.2

12

29

PSEN

(INT1)

P3.3

13

28

P2.0

(A15 )

(T0)

P3.4

14

27

P2.1

(A14 )

(T1)

P3.5

15

26

P2.2

(A13 )

(RD)

P3.6

16

25

P2.3

(A12 )

(WR)

P3.7

17

24

P2.4

(A11 )

XTAL2

18

23

P2.5

(A10 )

XTAL1

19

22

P2.6

(A9 )

GND

20

21

P2.7

(A8 )

3

Pins and Signals

3.2

Pin Description

The function of various pins are described below. It should be noted that, not all the features of 8051 can be used at the same time. Power supply and clock signals • VCC (Pin 40): +5 V power supply. • GND (Pin 20): Ground Reference. • XTAL1, XTAL2 (Pin 18,19): The 8051 has an on-chip oscillator but requires an external clock to run it. Most often a quartz crystal oscillator is connected to these pins. Ports 0,2 pins When external memory is connected to the 8051 microcontroller, Port 0 acts as the multiplexed lower-order address and data bus, while Port 2 acts as the higher-order address bus. • AD7 −AD0 (Pin 32-39): During the first part of a machine cycle, these pins function as the lower-order address bus (A7 −A0 ); and during the later part, these work as the data bus (D7 −D0 ). • A15 −A8 (Pin 21-28): These are the higher order address bus pins used in conjunction with demultiplexed A7 −A0 pins to get the 16-bit external memory address. If external memory is not used, Port 0 pins must be connected to 10KΩ pull-up resistor to function as simple I/O port. Port 2 does not need pull-up resistors and in the absence of external memory, work as simple I/O port.

4

Pins and Signals Port 3 pins Besides working as simple I/O port, these pins also provide some additional functions which are described below. • RXD, TXD (Pin 10,11): These pins are used to receive and transmit data serially with the help of on-chip UART controller. • INT0, INT1 (Pin 12,13): These pins are used for external hardware interrupts. • T0, T1 (Pin 14,15): When the timers in the microcontroller are configured as counters, these pins are used to provide external clock pulses. • RD, WR (Pin 16,17): These pins are used during data transfer (read or write) operations from external memory. Other pins • Port 1 (Pin 1-8): These are the dedicated 8-bit port pins of 8051. They do not serve any alternate function. • RST (Pin 9): This is the reset pin. This is often referred to as a power-on-reset and is implemented as shown below.

VCC

Reset button

C = 10µF

8051 µC 9 RST R = 8.2kΩ

5

Pins and Signals On reset, the values of 8051 registers are as follows. The ports are configured as input ports and the register bank selected is RB0. Register

Reset value

Program Counter

0000H

Data Pointer

0000H

Accumulator

00H

Program Status Word

00H

Stack Pointer

07H

B-register

00H

Ports P0–P3

FFH

• EA/VPP (Pin 31): It stands for “external access". If this pin is low, then 8051 will access instructions (opcodes) from externally connected memory only. If this pin is held high, 8051 executes programs from memory locations 0000H to 0FFFH of internal ROM and from memory locations 1000H to FFFFH of external ROM/RAM. • PSEN (Pin 29): This is an output pin and stands for “program store enable". This pin is used when EA = 0 signifying that the instructions are stored in external memory. It is connected to output enable pin of external ROM. • ALE/PROG (Pin 30): When Port 0 is used in its alternate mode (as the multiplexed data bus and lower-order address bus), Address Latch Enable is used to demultiplex them. This pin is also used for programming input pulse for EPROM versions of 8051.

6

Memory Organisation

4

Memory Organisation

8051 implements a separate memory space for programs (code) and data. These code and data memory is internal and limited; however both can be expanded to a maximum of 64KB. The internal memory of 8051 consists of a 4KB on-chip ROM which is used as program memory, and a 256 bytes on-chip RAM which is used as data memory. The on-chip RAM contains a rich arrangement of general-purpose storage, bit-addressable storage, register banks, and special function registers. Both program and data memory can be expanded to a maximum of 64KB as shown below. FFFFH

FFFFH External RAM

External ROM

FFH

1000H 0FFFH

SFR 128 bytes

EA = 0 80H

Internal ROM EA = 1 4KB

0000H

64KB

Internal RAM 128 bytes

64KB 00H

PROGRAM MEMORY

4.1

7FH 0000H

DATA MEMORY

Program Memory

If EA pin is connected to GND, it indicates that the program is stored in the externally connected ROM. All the opcodes are fetched from the memory locations 0000H to FFFFH of the external ROM. If EA pin is connected to VCC , 8051 accesses instructions from the 4KB internal ROM first; then, when it reaches the end of the on-chip ROM it switches to the external ROM for the rest of the instructions. In other words, 8051 fetches opcodes starting from 0000H , then goes on to address 0FFFH (the last location of on-chip ROM); after that the opcodes are fetched from the address 1000H to FFFFH of the external ROM. Here, PSEN pin is connected to the OE (output enable) pin of the external ROM. 7

Memory Organisation

4.2

Data Memory

To access data from external 64KB RAM, specific instructions are used, the most common being MOVX. Here RD and WR pins are connected to the OE (output enable) pin and WE (write enable) pin of external RAM respectively.

The internal data memory organisation is as follows. I. General purpose RAM: These are user-accessible general purpose storage area addressed from 00 to 7FH . These 128 bytes are divided into three different groups as follows: 1. Working Registers: A total of 32 bytes from locations 00H to 1FH are set aside for registers. These are organised as four banks of eight registers each. The four register banks are numbered 0 to 3 and are made up of eight registers named R0 to R7. Each register can be addressed by name (when its bank is selected) or by its RAM address. Register bank selection is done by programming the RS1 and RS0 bits of Program Status Word. RS1

RS0

Bank selected

Address

0

0

RB0, default

00H –07H

0

1

RB1

08H –0FH

1

0

RB2

10H –17H

1

1

RB3

18H –1FH

2. Bit-Addressable Registers: A total of 16 byes from locations 20H to 2FH are set aside for Bit-Addressable Registers, forming a total of 128 (16 locations, each of 8 bits) addressable bits. An addressable bit may be specified by its bit address (00H − 7FH ) or 8 bits may form any byte address from 20H to 2FH . Depending on the instructions, the microcontroller will address a bit or one of the working registers. 3. General Purpose: A total of 80 bytes from locations 30H to 7FH are used for general read and write storage, or what is normally called a scratch pad. As Stack Pointer is of 8 bit, Stack is implemented using this general purpose area of internal memory. 8

Memory Organisation

1F

7F

R7

· · ·

Register Bank 3

18

R0

17

R7

· · ·

Register Bank 2

R7

· · ·

Register Bank 1

08

R0

07

R7

· · ·

Register Bank 0

00

R0 Working Registers

2F

7F

2E

77

78

08

· · ·

0F

· · ·

R0

· · · · · ·

10

00

70

· · · · · · · · 21

0F

20

07

Bit-Addressable Registers

· · · · · · · · · · · · · · · · · · · · · · · ·

Scratch-Pad Memory

Stack

30 General Purpose

II. Special function Registers: Out of the 128 bytes reserved, 8051 uses only 21 special function registers. These SFRs can be accessed by their names or by their addresses. Some of the SFRs also support bit addressing. All these registers have specific predefined functions. These registers are like the control words of various chips; and by initializing them accordingly, 8051 can be operated in various modes. The list of 8051 SFRs is shown below. Name

Function

Address

A*

Accumulator

E0H

B* DPTR (DPH, DPL)

Multiply and divide operation Data pointer for external access

F0H 83H , 82H

IE*

Interrupt enable control

A8H

IP*

Interrupt priority control

B8H

P0–P3*

I/O Ports

80H , 90H , A0H , B0H

PCON PSW*

Power control Program status word

87H D0H

SCON*

Serial control

98H

SBUF

Serial data buffer

99H

SP

Stack pointer

81H

TMOD

Timer/counter mode selection

89H

TCON* TH0, TL0

Timer/counter control Timer 0 data

88H 8CH , 8AH

TH1, TL1

Timer 1 data

8DH , 8BH

*These SFRs support bit-addressing.

9

Memory Organisation Data pointer The data pointer (DPTR) is used to access external code or data memory. It is a 16-bit register which holds the address of the externally connected memory from where data is to be accessed. 8051 supports instruction where DPTR can be initialized either as a 16-bit register or as 2 8-bit registers—DPH and DPL. Program Status Word The 8-bit format of PSW register in 8051 microcontroller is shown below. D7

D6

D5

D4

D3

D2

CY

AC

F0

RS1

RS0

OV

D1 D0 –

P

Bit PSW.7

Symbol CY

Bit Address Description D7H Carry Flag

PSW.6

AC

D6H

Auxiliary carry Flag

PSW.5

F0

D5H

General purpose, user defined flag

PSW.4

RS1

D4H

Register bank select 1

PSW.3

RS0

D3H

Register bank select 0 00 = Register bank 0, default 01 = Register bank 1 10 = Register bank 2 11 = Register bank 3

PSW.2

OV

D2H

PSW.1

−

−

PSW.0

P

D0H

Overflow flag Reserved Even Parity flag

10

Addressing Modes

5

Addressing Modes

Addressing modes are an integral part of each computer’s instruction set. They allow specifying the source or destination data in different ways depending on the programming situation. The various 8051 addressing modes are discussed below.

5.1

Register Addressing

Register addressing mode involves the use of registers to hold the data to be manipulated. The 8051 programmer has access to 8 “working registers” numbered R0 through R7 for each of the 4 register banks. Other registers used are A, B, and DPTR. Examples include ADD A, R7 MOV A, R3 INC DPTR DIV AB Note: Data transfer between Rn registers is not allowed, i.e., MOV R1, R2 is an invalid instruction.

5.2

Direct Addressing

In direct addressing, the address of the operand is specified in the instruction. All 128 bytes of internal RAM (00H to 7FH ) as well as the SFRs (80H to FFH ) may be addressed directly using the 1-byte address assigned to them. For SFRs, the address may be given by its name also. For example, to transfer data from Port 0 to accumulator, we can either use Port 0’s address (80H ) or its name (P0). MOV A, 80h MOV A, P0 Some more examples MOV R0, 12h MOV 8Ch, R7 MOV 01h, PSW

11

Addressing Modes

5.3

Indirect Addressing

The indirect addressing mode uses registers R0, R1, and DPTR to point to the actual address from where data is to accessed. The mnemonic symbol used for indirect addressing is the “at” sign (@). For example, if R0 = 32h, then whatever data is present in the location 32h will be copied to the accumulator after the execution of MOV A,@R0. Other examples include MOV @R1, A MOVX A, @DPTR

5.4

Immediate Addressing

When a source operand is a constant, then the constant can be incorporated into the instruction as a byte of “immediate” data. In assembly language immediate operands are preceded by the “number” sign (#). For example, to load accumulator with a count value of 0Ah, we can use MOV A,#0Ah All instructions using immediate addressing use an 8-bit data constant for the immediate data. However, when initializing the data pointer, a 16-bit constant is required. For example, MOV DPTR,#8000h.

5.5

Relative Addressing

Relative addressing is used only with certain 2-byte jump instructions. The first byte specifies the opcode, and the second byte specifies the relative address or the offset. This offset has to be added to the program counter to get the address from where the next instruction is to be executed. The offset is specified as an 8-bit signed number; hence the range for jumping is −128 to +127, i.e, both forward and backward jumps are possible. For example, if the label THERE represents an instruction at location 8040H and the instruction SJMP THERE is in memory location 8000H and 8001H , the assembler will assign a relative offset of 3EH as byte 2 of the instruction (8002+3E = 8040H ).

12

Addressing Modes

5.6

Absolute and Long Addressing

Absolute addressing is used only with ACALL and AJMP instructions. These are 2-byte branching instructions which allow branching within the current 2K page of code memory. Out of the 16 bits of the destination address, only the lower 11 bits are specified within the 2-byte instruction. The higher 5 bits (A15 − A11 ) are fixed by the current page used. Long addressing is used only with LCALL and LJMP instructions. These are 3-byte branching instructions where the 1st byte specifies the opcode, and the 2nd and 3rd bytes specify the destination address. Absolute addressing offers the advantage of short (2-byte) instruction, but has the disadvantage of limiting the range for the destination. In long addressing, the full 64K code space may be used, but the disadvantage is that the instruction are three bytes long.

5.7

Indexed Addressing

Indexed addressing uses a base register (either the program counter or the data pointer) and an offset (the accumulator) in forming the effective address for a JMP or MOVC instruction. Examples are as follows. MOVC A, @A+DPTR MOVC A, @A+PC JMP @A+DPTR

5.8

Bit Addressing

The 8051 supports bit addressing through 210 bit-addressable locations, of which 128 (16×8) are at addresses 20H to 2FH , and the rest are in the special function registers. Using bit addressing, individual bits can be set, cleared, ANDed, ORed, etc., with a single instruction. The 128 general purpose bit-addressable locations (available in the memory space from 20H through 2FH ) are accessed using special singl...