Week 7: AVR Architecture PDF

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Summary

Practice questions on AVR Architecture, used alongside lecture...

Description

ELEC1601 Foundations of Computer Systems

School of Electrical and Information Engineering

Component

The University of Sydney

Description

Program Memory Program Counter Register File ALU Status Register Instruction Reg and Decoder Data Memory

ADD R2, R1

Memory

PC

Reg File

Mux + ALU

Status

IR Decoder

IF

ROF

ALU

RWB CPI R1, 15 IF

ROF

ALU

RWB 1

Week 7: AVR Architecture

ELEC1601 Foundations of Computer Systems

School of Electrical and Information Engineering

Time instruction i - 1

ROF

ALU

The University of Sydney

Time

RWB

FET: Instruction Fetch instruction i

IF

ROF

ALU

RWB

ID: Instruction Decode instruction i + 1

IF

ROF

ALU

RWB

Instruction Sequence

ROF: Register Operand Fetch

IF: Instruction Fetch

ALU: ALU Execution

ROF: Register Operand Fetch ALU: ALU Execution

Stage length = 100ms

RWB: Result Write Back

RWB: Result Write Back

Stage length = 100ms How long it takes to execute one instruction?

How many instructions are executed in parallel?

ADD R1, R2 SUB R3, R4 Must leave register file unchanged!

Modifies registers R1, R2 R3, R4 and R29 INC R29

How long does it take to execute an instruction? What is the interval between two instructions finishing?

What is the interval between two instructions finishing?

How many instructions are executing in parallel?

What happens with these two instructions: ADD R2, R1 ADD R3, R2 How do you decide the length in time?

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Week 7: AVR Architecture...