2018 assignment 4 delay sol PDF

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ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

Assignment 4.1 Q1: Sketch a 2-input NOR gate with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter. Compute rising/falling propagating delays of NOR gate driving h identical NOR gates using Elmore delay model. Assume every source or drain has fully contacted diffusion (count parasitic capacitance twice) when making your estimate of capacitance. Answer:

Fig. 1: 2-input NOR. If the 2 series PMOS do not share diffusion, and have their own contacts, the parasitic cap at the middle node of two PMOS will be 8C. Therefore the Elmore delay is: R 8C + R(6C + 5hC) = (10 + 5h)RC (1) 2 However, as there is no connection at the middle node of two PMOS, the diffusion will be shared by these two transistors if you try to make a stick diagram. The new Elmore delay will be: Dr =

R 4C + R(6C + 5hC) = (8 + 5h)RC 2

(2)

Df = R(6C + 5hC ) + R8C = (14 + 5h)RC

(3)

Dr = Falling edge Elmore delay is

Q2: Schetch a stick diagram for the 2-input NOR. Repeat Q1 with better capacitance estimates. If a diffusion node is shared between two parallel transistors, only budget its cap once. If a diffcusion node is between two series transistors and requires no contacts, only budget half the cap. Answer: The rising/falling Elmore delay is Dr =

R 2C + R(5C + 5hC ) = RC (6 + 5h) 2 Df = (5 + 5h)RC

(4) (5)

Q3: Plot a delay VS electrical effort graph for a 2-input NOR gate using simplified logic effort and parasitic delay summarized in the table. common gates, in slides. Compared woth 2-input NAND gate, which one is better in terms of delay? Page 1

ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

Fig. 2: Stick diagram for 2-input NOR.

Fig. 3: Normalized delay VS Electrical efforts of 2-input NOR.

Answer: Slop is 5/3 for NOR and 4/3 for NAND, and both have same parasitic delay. Therefore, NAND is better than NOR gates with respect to delay. Q4: Sketch a 4-input NAND gate with transistor width chosen to achieve equal rise and fall resistance as a unit inverter. What is logic effort? Answer: The logic effort is calculated based on the input cap of each input and the input cap of a unit inverter delivering the same current. The unit inverter has the size for 2 for PMOS and 1 for NMOS, and the corresponding current is VDD /2 for rising and falling transition. The input cap is 3. Therefore, the logic effort is: g = 6/3

(6) Page 2

ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

Fig. 4: 4-input NAND.

Q5: Consider two designs of a 2-input AND gate shown in Fig. 5. Intuitively, which one is better with respect to delay? Then prove your guess and calculate x and y to achieve this delay.

Fig. 5: 2-input AND gate. Answer: a) should be better than b) because by using bubble pushing, the output of b) is from a NOR gate, which inherently slower than NAND gate. For both: H =6

(7)

B=1

(8)

P =1+2

(9)

For a); 4 ∗ 1 = 4/3 3 F = GBH = 8

G=

1/2

f =8

(10) (11)

= 2.8

(12)

D = 2f + P = 8.6τ

(13)

x = 6C ∗ 1/f = 2.14C

(14)

For b); Page 3

ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

5 ∗ 1 = 5/3 3 F = GBH = 10

(16)

f = 101/2 = 3.2

(17)

D = 2f + P = 9.3τ

(18)

x = 6C ∗ (5/3)/f = 3.16C

(19)

G=

(15)

Q6: Some designer define a "gate delay" to be a fanout-of-3 (FO3)2-input NAND gate rather than a FO4 inverter. Using Logic effort, estimate the delay of a FO3 2-input NAND gate. Express your result both in τ and in FO4 inverter delays. Answer: The delay of FO4 is 5 τ , obtained from following calculation. d = gh + p = 1∗4+1 = 5τ

(20)

Now, we are using FO3 (fan-out-of 3)2-input NAND to represent the speed performance. The delay can be calculated by: d = gh + p = (4/3) ∗ 3 + 2 = 6τ

(21)

Normalized to FO4 inverter, the delay is 1.2 FO4 inverter. Q7: A 64-bit adder (6.6τ FO4 inverter) has a delay of 930 ps in a 0.5 µm process with an FO4 inverter delay of about 140 ps. Estimate its delay in a 65 nm process with an FO4 inverter delay of 20 ps. Answer: 6.6*20=132 ps Q8: The clock buffer in Fig. 6 can present a maximum input capacitance of 100 fF. Both true and complementary outputs must drive loads of 300 fF. Compute the input capacitance of each inverter to minimize the worst case delay from input to either output. What is this delay, in τ ? Assume the inverter parasitic delay is 1.

Fig. 6: Clock buffer. Answer: Since the maximum input cap is 100 fF, if upper inverter has size x, the lower inverter should be 100-x. To get the optimum delay, each stage should show the same stage effort. In other words, the second Page 4

ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

inverter of the upper chain should have the same stage effort as the first inverter of the upper chain. G=1, H = 300/x, B = 1. The bottom inverter must show the same delay as the upper chain. Then we can write equation as below:

2∗

s

(

300 300 )+2= +1 x 100 − x (22)

, we know the Solve the equation for x, we can get x = 49.4, and D = 6.9τ . According to f = g CCout in load is 300fF, and we know the stage effort is 2.45. Then, we can have the size for the second inverter of upper chain, 122. Because the input cap is 100 fF. The size of lower inverter is 50.6, leading to stage effort of 6.9τ . Q9: Consider four designs of a 6-input AND gate shown in Fig. 8. What design is fastest for electrical effort, H=1, H=5 and H=20? Show the calculated minimum delay for each cases.

Fig. 7: 6-input AND. Answer: Design b) is fastest for H=1 or 5. Design d) is fastest for H=20 because it has a lower logic effort and more stages to drive the large path effort. c) is always worse than b) because it has greater logical effort, all else being equal(all the delay is based on τ ).

Page 5

ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

Fig. 8: 6-input AND.

Q10: A 3-stage logic path is designed so that the stage effort of each stage is 12, 6, and 9 delay units respectively. Please answer the following questions: 1) Can this design be improved in terms of speed? And how if yes? And why if no? 2) What is the best number of stages for this path? 3) What changes do you recommend to the existing design? Answer: 1) The answer is yes. The design can be improved in terms of speed. The optimum stage effort resulting in least delay is between 2.4 to 6. In this course, we choose 4. So, imbalanced delay of each stages can be changed to the balanced delay such that better timing performance can be achieved. 2) According the equation, the best number of stages is = log4F , where F = 12*6*9=648. Therefore, N is chosen as 5. 3) Simply adding two inverts at the output will be enough. The delay now becomes D=5*f+2=5*648( 15)+2=20.2 As compared to 12+6+9=27, this improvement is significant. Q11: Sketch a transistor level circuit for a AND-OR-INVERTER(AOI21). Label the size of the PMOS and NMOS. Draw a stick digram, labelling the diffusion capacitance. Estimate propagation delay using Elmore delay model(Note:consider series connected transistor has shared one contact). Answer: Fig. 9 shows the transistor level circuit and the associated stick diagram. The size is labelled in accordance with the equal rising and falling resistance. Now let us find out the worst case for charging and discharching of the diffusion capacitor at the output, Y. As we are required to use Elmore delay model to estimate the delay, the branch node, therefore, should be included. In Fig. 9 a, blue line represents the worst charge path. And the red line represents the worst discharge path. tpdr = (R/2) × 8C + (R/2 + R/2) × 7C + (R/2 + R/2) × 2C = 13RC

tpdf = (R/2) × 2C + (R/2 + R/2) × 7C = 8RC Q12: The output pad contains a chain of successively larger inverters to drive enormous off-chip capacitance. If the first inverter in the chain has an input capacitance of 20 fF and the off-chip load Page 6

ENGI4054:Digital VLSI Circuit Design

Yushi Zhou ([email protected])

Fig. 9: AOI. a) transistor level circuits, and b) stick diagram with shared diffusion capacitance

is 10 pF, how many inverters should be used to drive the load with least delay? Estimate this delay, expressed in FO4 inverters delay. Answer: F=10 pF/20 fF = 500. N=log 4F =4.5.Therefore, stage number 5 should work if the polarity of the output is acceptable. D=4F1/4 +4=22.9 τ =4.58 FO4 delay.

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