Advanced Digital design verilog SV modified PDF

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Advanced Digital Design using Verilog and Verification (4-0-0-0-4) Course Objectives: ● The course intended to enhance the skill set of the students in RTL coding, FSM design using Verilog and System Verilog for Verification. This course also equip the students to understand hardware verfication language lexical elements of System Verilog and its application in Digtial design verification. Course Outcomes: Students completing the course should be able to ● Good RTL design and FSM design using Verilog ● Good understanding of System Verilog and writing effective system Verilog testbenches. ● Writing System Verilog Assertions. Course Content: 1. RTL coding using Verilog HDL: RT level Combination Circuit, Regular Sequential circuit, FSM, FSMD and Selected topics in Verilog. (Reference -I). 2. Advanced Digital Design Concepts: Metastability, Clocks and Resets, Clock dividers, Clock Domain crossing, Low power design. (Reference -II, Reference III, Reference VII). 3. System on Chip: - System on Chip (SOC) Design, SOC Constituents, SOC Synthesis, Static Timing Analysis (STA). (Reference -III). 4. System Verilog for Verification: - SOC Design Verification, Basic OOP of System Verilog, Threads and IPC, Randomiztion, Code coverage, Functional coverage, Advanced OOPs and testbench guidelines, Complete System verilog testbench. Design Verification examples for complete system verilog layered testbench (Reference -IV). 5. System Verilog Assertions: System Verilog Assertions, Immediate Assertions, Concurrent Assertions, System Verilog Semantics, Operators, Sampled Value Functions, System functions and tasks, Multiple clocks, “assume”, “expect”, Local variables and recursive property, Asynchronous assertions. (Reference -V and VI). Pre-requisite Courses: Digital Design/Logic design. Reference Books: 1. Pong P Chu, “FPGA Prototyping by Verilog Examples: Xilinx Sparta-3 Version”, Wiley Blackwell, ISBN-13: 978-0470185322, 2008. 2. Mohit Arora, “The Art of Hardwre Architecture: Design Methods and Techniques for Digital Circuits”, Springer-2012, ISBN-13: 978-1461403968. 3. Veena S Chakravarthi, “A Practical Approach to VLSI System on Chip (SoC) Design: A Comphrehensive Guide”, Springer, 1st edition, 2020, ISBN 978-3-030-23049-4. 4. Chris Spear and Greg Tumbush, “System Verilog for Verification”, Springer, 3 rd edition, ISBN: 978-1461407140, 2012. 5. Ashok Mehta “System Verilog Assertions and Functional Coverage: Guide to language, methodoloby and applications” , Springer, ISBN-13: 978-1461473237, 2013. 6. Clifford E Cummings, Arturo Salz, “System Verilog Event Regions, Race Avoidance and Guidelines”, Sunburst Design Inc White paper. http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf. 7. Clifford E Cummings, “:Clock Domain Crossing (CDC) Design & VerificationTechniques”, http:// www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf....