CPSC 240 L14V7-Floating-Point Processing and Instruction Encoding(Chpt 12) PDF

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Professor's name was Eric Shulman....

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CPSC 240_L14V7-Floating-Point Processing and Instruction Encoding(Chpt 12).docx 12-24-2016 This lecture is from Chapter 12 in Kip Irvine’s Assembly Language of X86 Processors 6th Ed, his supplemental instruction material, and other sources. Added in new section 2.6 on Additional Floating Point Instructions & page 6 example correction Table of Contents 1

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Floating-Point Binary Representation ....................................................................................................................... 2 1.1 IEEE Floating-Point Binary Reals ........................................................................................................................ 2 1.2 Normalized Binary Floating-Point Numbers .................................................................................................. 3 1.3 Creating the IEEE Representation ...................................................................................................................... 4 1.3.1 NaNs (Not-A-Number)..................................................................................................................................... 4 1.4 Converting Decimal Fractions to Binary Reals .............................................................................................. 5 1.5 Converting Single-Precision to Decimal ........................................................................................................... 5 Floating-Point Unit ............................................................................................................................................................ 6 2.1 FPU Register Stack .................................................................................................................................................... 6 2.2 Rounding ....................................................................................................................................................................... 8 2.3 Floating-Point Exceptions ...................................................................................................................................... 8 2.4 Floating-Point Instruction Set .............................................................................................................................. 9 2.4.1 Floating Point Instruction Set Data Types ............................................................................................... 9 2.4.2 Load Floating-Point Value (FLD) .............................................................................................................. 10 2.4.3 Store Floating-Point Value (FST, FSTP) ................................................................................................. 10 2.5 Arithmetic Instructions ........................................................................................................................................ 11 2.5.1 Floating-Point Add (FADD) – Add source to destination ................................................................ 11 2.5.2 Floating-Point Subtract (FSUB) ................................................................................................................ 12 2.5.3 Floating-Point Multiply (FMUL) ............................................................................................................... 12 2.5.4 Floating-Point Divide (FDIV) ..................................................................................................................... 13 2.6 Additional Floating Point Instructions ........................................................................................................... 13 2.7 Comparing Floating-Point Values .................................................................................................................... 15 2.8 Reading and Writing Floating-Point Values................................................................................................. 17 2.9 Exception Synchronization ................................................................................................................................. 17 2.10 Mixed-Mode Arithmetic ..................................................................................................................................... 18 2.11 Masking and Unmasking Exceptions ............................................................................................................ 18 Addition Floating Point Information and Instructions ..................................................................................... 20 3.1 FPU Registers, Control Word, Status Word, and Tag Word ................................................................... 20 3.2 FPU Additional Instructions ............................................................................................................................... 28 x86 Instruction Encoding ............................................................................................................................................. 37 4.1 x86 Instruction Format ........................................................................................................................................ 37 4.2 Single-Byte Instructions ....................................................................................................................................... 38 4.3 Move Immediate to Register .............................................................................................................................. 39 4.4 Register-Mode Instructions ................................................................................................................................ 39 4.5 x86 Processor Operand-Size Prefix ................................................................................................................. 40 4.6 Memory-Mode Instructions ................................................................................................................................ 41 Summary ............................................................................................................................................................................ 43

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1 Floating-Point Binary Representation A floating-point number contains three components: a sign, a significand, and as exponent. In the number -1.23254 x 105 The sign is negative The signficand is 1.23154 The exponent is 5 Note: Even though it is slightly less correct, the term mantissa is often substituted for the term significand 1.1 IEEE Floating-Point Binary Reals IEEE Floating-Point Binary Formats

Single-Precision Format Approximate normalized range: 2–126 to 2127. Also called a short real. 1

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23

exponent

fraction

sign

Components of a Single-Precision Real • Sign (1 = negative, 0 = positive) • Significand - decimal digits to the left & right of decimal point, a weighted positional notation 23 bits in length Example: 123.154 = (1 x 102) + (2 x 101) + (3 x 100) + (1 x 10–1) + (5 x 10–2) + (4 x 10–3) • Single precision exponents are stored as 8-bit unsigned integers with a bias of 127. • The number’s actual exponent must be added to 127. For example, the binary value 1.101 x 105 The actual exponent would be 127 + 5 or 132, which would be stored in the number’s representation. We add the actual exponent 5 to the bias of 127 and get 132. The biased exponent is always positive (between 1 and 254). Noting that the actual exponent range is from -126 to +127. This range was chosen so that the smallest possible exponent’s reciprocal can not cause an overflow. 2

Sample Exponents Represented in Binary

Decimal Fractions vs Binary Floating-Point This should be review. We covered this in CPSC 240_L3 Binary Arithmetic

1.2 Normalized Binary Floating-Point Numbers Most floating-point numbers are stored in normalized form so as to maximize the precision of the significand (often called the mantissa). • Mantissa is normalized when a single 1 appears to the left of the binary point • Unnormalized: shift binary point until exponent is zero

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1.3 Creating the IEEE Representation Once the sign bit, exponent and significand fields are normalized and encoded, it is easy to generate a complete binary IEEE short real. 1

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exponent

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fraction

sign

Example 1 (IEEE short real-Single Precision) 1.101 x 20 Sign bit: 0 (Positive) Exponent: 01111111 (127 in binary) Fraction: 10100000000000000000000 (23 bits) Note: All normalized significands have a 1 to the left of the binary point, so there is no need to explicitly encode the bit. Examples of Single Precision Encodings

1.3.1 NaNs (Not-A-Number) NaN’s are bit patterns that do not represent any valid real numbers. There are two types of NaNs Quiet NaN can propagate through most arithmetic operations without causing an exception. Signaling NaN can be used to generate a floating-point invalid operation exception. A compiler might fill an uninitialized array with signaling NaN values so that any attempt to perform calculations on the array will generate an exception. A quiet NaN can be used to hold diagnostic information created during debugging sessions. A program is free to encode any information in a NaN it wishes to. The FPU (Floating-Point Unit) does not attempt to perform operations on NaN’s.

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Specific encodings (Single Precision)

1.4 Converting Decimal Fractions to Binary Reals This should be review. We covered this in CPSC 240_L3 Binary Arithmetic Express as a sum of fractions having denominators that are powers of 2 For example

1.5 Converting Single-Precision to Decimal 1. If the MSB is 1, the number is negative; otherwise, it is positive. 2. The next 8 bits represent the exponent. Subtract binary 01111111 (decimal 127), producing the unbiased exponent. Convert the unbiased exponent to decimal. 3. The next 23 bits represent the significand. Notate a “1.”, followed by the significand bits. Trailing zeros can be ignored. Create a floating-point binary number, using the significand, the sign determined in step 1, and the exponent calculated in step 2. 4. Unnormalize the binary number produced in step 3. (Shift the binary point the number of places equal to the value of the exponent. Shift right if the exponent is positive, or left if the exponent is negative.) 5. From left to right, use weighted positional notation to form the decimal sum of the powers of 2 represented by the floating-point binary number. The website below illustrates IEEE 754 with a working converter https://www.h-schmidt.net/FloatConverter/IEEE754.html 5

Example Convert 0 10000010 01011000000000000000000 to Decimal 1

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exponent

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fraction

sign

1. The number is positive. 2. The unbiased exponent is binary 00000011, or decimal 3. 1000 0010 – 0111 1111 = 0000 0011 3. Combining the sign, exponent, and significand, the binary number is +1.01011 X 23. 4. The unnormalized binary number is +1010.11. 5. The decimal value is +10 3/4, or +10.75.

2 Floating-Point Unit 2.1 FPU Register Stack  The FPU does not use the general-purpose registers (EAX, EBX, etc).  It has its own set of registers called a register stack.  It loads values from memory into the register stack, performs calculations, and stores stack values into memory. • The FPU Register Stack contains eight individually addressable 80-bit data registers named R0 through R7 • Three-bit field named TOP in the FPU status word identifies the register number that is currently the top of stack. In the diagram to the right, TOP equals a binary 011, which identifies R3 as the top of the stack. This stack location is also known as ST(0) (or simply ST) when writing floating-point instructions. The last register is ST(7). A push operations (also called a load) decrements TOP by 1 and copies an operand into the register identified at ST(0). If TOP equals 0 before a push, TOP wraps around to register R7. A pop operations (also called a store) copies the data at ST(0) into an operand, then adds 1 to TOP. If TOP equals 7 before the pop, it wraps around to register R0. If loading a value into the stack would result in overwriting existing data in the register stack, a floating-point exception is generated. 6

The diagram below shows the same stack after 1.0 and 2.0 have been pushed (or loaded) onto the stack.

We will only be focusing on ST(n) notation. ST(0) is always the top of the stack. We will be referring to stack registers as ST(), ST(1), etc. Instruction operands can not refer directly to register numbers. Floating-point values in registers use the IEEE 10-byte extended real format (also called temporary real). When the FPU stores the result of an arithmetic operation in memory, it translates the result into one of the following formats integer, long integer, single precision (short real), double precision (long real), or packed binarycoded decimal (BCD). The FPU has six special-purpose registers • Opcode register: stores opcode of last noncontrol instruction executed • Control register: controls precision and rounding method for calculations • Status register: top-of-stack pointer, condition codes, exception warnings • Tag register: indicates content type of each register in the register stack It uses 2-bits per register to indicate whether the register contains a valid number, zero, or a special value (NaN, Infinity, denormal, or unsupported format) or is empty • Last instruction pointer register: pointer to last non-control executed instruction • Last data (operand) pointer register: points to data operand used by last executed instruction

The special-purpose registers are used by operating systems to preserve state information when switching between tasks.

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2.2 Rounding • FPU attempts to round an infinitely accurate result from a floating-point calculation may be impossible because of storage limitations • Example suppose 3 fractional bits can be stored, and a calculated value equals +1.0111. rounding up by adding .0001 produces 1.100 rounding down by subtracting .0001 produces 1.011 The FPU lets you select one of four rounding methods Round to nearest even: The rounded result is the closest to the infinitely precise result. If two values are equally close, the result is an even value (LSB=0) Round down toward - : The rounded result is less than or equal to the infinitely precise result Round up toward+ : The rounded result is greater than or equal to the infinitely precise result. Round toward zero: (also known as truncation), The absolute value of the rounded result is less than or equal to the infinitely precise result.

2.3 Floating-Point Exceptions In every program, things can go wrong, and the FPU has to deal with the result of this. • Six types of exception conditions Invalid operation (#I) Divide by zero (#Z) Denormalized operand (#D) Numeric overflow (#O) Numeric underflow (#U) Inexact precision (#P) The first three exceptions (#I, #Z, #D) are detected before any arithmetic operation occurs. 8

The later three exceptions (#O, #U, #P) are detected after an operation occurs. Each excerption type has a corresponding flag bit and mask bit. When a floating-point exception is detected, the processor sets the matching flag bit. For each exception flagged by the processor, there are two courses of action • If the corresponding mask bit is set, the processor handles the exception automatically and lets the program continue • If the corresponding mask bit is clear, the processor invokes a software exception handler. 2.4 Floating-Point Instruction Set The FPU instruction set contains the following basic categories of instructions Data Transfer Basic arithmetic Comparison Transcendental (e.g., FSIN) Load constants (specialized predefined constants only) X87 FPU control X87 FPU and SIMD state management • Instruction mnemonics begin with letter F • Second letter identifies data type of memory operand B = bcd I = integer no letter: floating point • Examples FLBD load binary coded decimal FISTP store integer and pop stack FMUL multiply floating-point operands A floating-point instruction can have zero, one, or two operands. If there are two operands, one must be a floating-point register. There are no immediate operands, but certain predefined constants (such as 0.0, Pi, and log 2 10) can be loaded into the stack. General purpose registers such as EAX, EBX, ECX, and EDX can not be operands. The only exception is FSTSW, which stores the FPU status word in AX Memory-to-memory operations are not permitted. 2.4.1 Floating Point Instruction Set Data Types

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2.4.2 Load Floating-Point Value (FLD) FLD - Copies floating point operand from memory into the top of the FPU stack, ST(0). The operand can be a 32-bit, 64-bit, or 80-bit memory operand (REAL4, REAL8, REAL10) or another FPU register. FLD supports the same memory operand types as the MOV instruction. FLD FLD FLD FLD

m32fp m64fp m80fp ST(i)

; Is the REAL4 memory operand ; Is the REAL8 operand ; is the REAL10 operand ; I is the register number

The code below illustrates the memory operand types .data array REAL8 10 DUP (?) .code fld array ; direct fld [array + 16} ; direct-offset fld REAL8 PTR[esi] ; indirect fld array[esi] ; indexed fld array[esi*8] ; indexed, scaled ; and others Remember that Real8 PTR – The size of the target operand Example

The figure below shows the stack contents of FPU after executing the above instructions

2.4.3 Store Floating-Point Value (FST, FSTP) FST - Copies floating point operand from the top of the FPU stack into memory FSTP – Pops the stack after copying FST FST FST

m32fp m64fp ST(i)

; Is the REAL4 memory operand ; Is the REAL8 operand ; I is the register number 10

2.5 Arithmetic Instructions The basic arithmetic operations are listed below. Arithmetic instructions all support the same memory operand types as FLD (load) and FST (store), so operands can be indirect, indexed, base-index, etc.

2.5.1 Floating-Point Add (FADD) – Add source to destination FADD FADD m32fp ; Is the REAL4 memory operand FADD m64fp ; Is the REAL8 operand FADD ST(0), ST(1) FADD ST(1), ST(0) No Operands If no operands are used with FADD, ST(0) is added to ST(1) The result is temporarily stored in ST(1) ST(0) is then popped from the stack, leaving the result on the top of the stack. Refer to the diagram below

Register Operands Starting with the same stack contents as above, the following illustration demonstrates adding ST(0) to ST(1)

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Memory Operand When used with a memory operand, FADD adds the operand to ST(0) as in fadd mySingle ; ST(0) += mySingle fadd REAL8 PTR[esi] ; ST(0) +=[esi] Just like in C++ ST(0) += mySingle is equal to ST(0) = ST(0) + mySingle 2.5.2 Floating-Point Subtract (FSUB)  The FSUB instruction subtracts a source operand from a destination operand, storing the difference in the destination operand.  The destination is always an FPU register, and the source can be either an FPU register or memory.  It accepts the same operands as the FADD instruction FSUB FSUB FSUB FSUB FSUB

m32fp m64fp ST(0), ST(i) ST(i), ST(0)

; Is the REAL4 memory operand ; Is the REAL8 operand ; I is the register number

FSUB’s operation is similar to that of the FADD operation except that it subtracts rather than adds. No-Operand If no operands are used, FSUB subtracts ST(0) from ST(1). The result is temporarily stored in ST(1). ST(0) is then popped from the stack, leaving the result on the top of the stack. With a Memory Operand FSUB with a memory operand subtracts the memory operand from ST(0) and does not pop the stack. Example fsub mySingle fsub array[edi*8]

; ST(0) -= mySingle ; ST(0) -= array[edi*8]

2.5.3 Floating-Point Multiply (FMUL)  The FMUL instruction multiplies a source...