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Aaditya Bhetuwal

20BDS0406

Course: Digital Logic and Design – ELA

Experiment-5: ADDERS, SUBTRACTORS AND MAGNITUDE COMPARATORS

Name: Aaditya Bhetuwal Regd. No.: 20BDS0406

Aaditya Bhetuwal

20BDS0406

Experiment-3: ADDERS, SUBTRACTORS AND MAGNITUDE COMPARATORS OBJECTIVE: • To construct and test various adders and subtractor circuits. • To construct and test a magnitude comparator circuit.

APPARATUS: − IC type 7486 quad 2-input XOR gates − IC type 7408 quad 2-input AND gates − IC type 7404 HEX inverter − IC type 7483 4-bit binary adder − IC type 7485 4-bit magnitude comparator.

Aaditya Bhetuwal

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TASK-a: Half adder using XOR and NAND Aim: To design a half adder using only XOR and NAND gate. Software used: ORCAD (Capture CIS lite)

Question: Design using OrCAD a half adder circuit using only XOR gates and NAND gates. Then during the Lab construct the circuit and verify its operation. Solution:

The truth table for the given question for detecting invalid BCD code is:

Input A 0 0 1 1

Output B 0 1 0 1

S 0 1 1 0

Ci 0 0 0 1

So, we can write, S = ∑m (1, 2), Ci = ∑m (3)

For Ci, we don’t need K-map, so, Ci = A.B

Aaditya Bhetuwal Also, we don’t need K-map for S. So, S = A’.B + A.B’ So, S = A ⊕ B,

Here, Ci = A.B,  Ci = ((A.B)’)’

So, the Half adder using only XOR and NAND gates is,

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Aaditya Bhetuwal Result

Inference: Hence, we implemented a half adder using only XOR and NAND gates.

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Aaditya Bhetuwal

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TASK-b: Full adder using XOR and NAND Aim: To design a full adder using only XOR and NAND gate. Software used: OrCAD (Capture CIS lite)

Question: Design using OrCAD a full adder circuit using only XOR gates and NAND gates. Then during the Lab construct the circuit and verify its operation.

Solution:

The truth table for a full adder (3-bit adder is) is:

A 0 0 0 0 1 1 1 1

Input B 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

So, we can write, S = ∑m (1, 2, 4, 7), Ci = ∑m (3, 5, 6, 7)

Output S Cout 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

Aaditya Bhetuwal K-map for S

So, S = A'.B.C' + A.B'.C' + A'.B'.C + A.B.C Which, can be written as S=A⊕B⊕C

K-map for Cout

So, Cout = B.C + A.C + A.B

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Aaditya Bhetuwal Here, Cout = B.C + A.C + A.B,  Cout = ((B.C + A.C + A.B)’)’ (negation law (A’)’ = A)  Cout = ((B. C)’. (A. C)’. (A. B)’)’

So, the Full adder using only XOR and NAND gates is,

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Aaditya Bhetuwal Result

Inference: Hence, we implemented a full adder using only XOR and NAND gates.

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Aaditya Bhetuwal

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TASK-c: 4-bit adder using IC 7483 Aim: To design a full adder using only XOR and NAND gate. Software used: OrCAD (Capture CIS lite)

Question: Use IC 7483 to add the two 4-bit numbers A and B shown in Table1. In OrCAD, select the chip 74-83 and use Binary switches for the bits of the two numbers and the input carry and use Binary Probe for the sum and carry out. A3

A2

A1

A0

B3

B2

B1

B0

1

0

0

1

0

0

1

0

0

1

1

0

1

0

1

1

1

1

0

0

1

0

1

0

Sum

Carry out

Input carry Ci is taken as logic 0. Show that if the input carry is 1, it adds 1 to the output sum. In the Lab use switches S1-1 to S1-8 for the two numbers and use the SPDT S2 for the input carry Ci. For sum and carry out, use LED-1 to LED-5. Solution:

Aaditya Bhetuwal

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The truth table for a full adder (3-bit adder is) is:

A 0 0 0 0 1 1 1 1

Input B 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

Output S Cout 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

Here, we will have 8 inputs i.e., from A4 to A1 and B4 to B1, which means 28 = 256 combinations for inputs for a 4-bit adder implemented using IC 7483, So, we only write the truth table for those inputs given in the question.

Aaditya Bhetuwal Circuit

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Aaditya Bhetuwal Result

So, the Full adder using only XOR and NAND gates is, For adding, C0 is LOW(0).

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Aaditya Bhetuwal Result

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Aaditya Bhetuwal Now, to fill the given table in question,

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Aaditya Bhetuwal

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Aaditya Bhetuwal

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Now, we can fill in the table when C0 = 0, Sum A3

A2

A1

A0

B3

B2

B1

B0 S4

S3

S2

S1

Carry out

1

0

0

1

0

0

1

0

1

0

1

1

0

0

1

1

0

1

0

1

1

0

0

0

1

1

1

1

0

0

1

0

1

0

0

1

1

0

1

Aaditya Bhetuwal Here, if we supply C0 as 1(HIGH) in the input circuit. We get,

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Aaditya Bhetuwal

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Aaditya Bhetuwal

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Output if, C0 = 1 Sum A3

A2

A1

A0

B3

B2

B1

B0 S4

S3

S2

S1

Carry out

1

0

0

1

0

0

1

0

1

1

0

0

0

0

1

1

0

1

0

1

1

0

0

1

0

1

1

1

0

0

1

0

1

0

0

1

1

1

1

As, we can see from the two tables (when C0 = 0 and C0 = 1), sum when C0 is 1 = (sum when C0 = 0 + 1)

Inference: Hence, we used IC 7483 to add two 4 bits numbers and get the carry out and proved that sum when C0 is 1 is (sum when C0 is 0 + 1) added to the sum.

Aaditya Bhetuwal

20BDS0406

TASK-d: To carry out operations given in table Aim: To use IC 7483 to perform addition and subtraction of two 4-bit

numbers. Software used: OrCAD (Capture CIS lite)

Question: Connect the adder-subtractor circuit as shown in Fig 2. Perform the following operations and record the values of the output sum and the output carry Co. Decimal A B 9+5

Output sum

Carry Out Co

9-5 9 + 13 9-9 10 + 6 6 - 10

A. Show that Co =1 when sum exceeds 15. B. Comment on sum and Co for the subtraction operations when A > B and A < B. Solution:

Aaditya Bhetuwal Circuit for Addition i.e., (C0 = 0)

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Aaditya Bhetuwal Circuit for Subtraction i.e., (C0 = 1)

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Aaditya Bhetuwal Result i.

9+5

Here, 9 + 5 = 1001 + 0101 For addition C0 = 0

1001 + 0101 = 1110, C4 = 0.

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Aaditya Bhetuwal ii.

9–5

Here, 9 – 5 = 1001 – 0101  9 – 5 = 1001 + 1010 + 1  i.e., C0 = 1.

So, 1001 – 0101 = 0100  9 – 5 = 4 and C4 = 1

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Aaditya Bhetuwal iii.

9 + 13

Here, 9 + 13 = 1001 + 1101, and For addition C0 = 0,

So, 1001 + 1101 = 0110 And C4 = 1.

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Aaditya Bhetuwal iv.

9–9

Here, 9 – 9 = 1001 – 1001  9 – 9 = 1001 + (1001)’ + 1 For subtraction, C0 = 1.

So, 1001 – 1001 = 0000, And C4 = 1.

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Aaditya Bhetuwal v.

10 + 6

Here, 10 + 6 = 1010 + 0110, For addition C0 = 0,

So, 1010 + 0110 = 0000 And C4 = 1

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Aaditya Bhetuwal vi.

6 – 10

Here, 6 – 10 = 0110 – 1010 For subtraction, C0 = 1,

Here, 0110 – 1010 = 1100 i.e., 6 – 10 = -4(2’s complement of 4 = 1100) and C4 = 0

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Aaditya Bhetuwal

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9+5

Binary equivalent (A and B) A B C0 1001 0101 0

S4 1

S3 1

S2 1

S1 0

9-5

1001

0101

1

0

1

0

0

1

9 + 13

1001

1101

0

0

1

1

0

1

9-9

1001

1001

1

0

0

0

0

1

10 + 6

1010

0110

0

0

0

0

0

1

6 - 10

0110

1010

1

1

1

0

0

0

Decimal (A and B)

Output sum

Carry Out (Cout) 0

A. Show that Co =1 when sum exceeds 15.  When, sum exceeds 15, C4 or Cout = 1, we can see that when we add 9 + 13, we get 0110(6) as sum and Co = 1.

B. Comment on sum and Co for the subtraction operations when A > B and A < B.  When A > B, for subtraction, the result is positive and end carry is generated, i.e., Cout = 1.  When A < B, the result is in it’s 2’s complement form and end carry is not generated.

Inference: Hence, we used IC 7483 to add or subtract various 4-bit numbers.

Aaditya Bhetuwal

20BDS0406

TASK-e: Magnitude Comparator Aim: To use IC 7485 to compare two 4-bit numbers. Software used: OrCAD (Capture CIS lite)

Question: Use IC7485 to compare the following two 4-bit numbers A and B. Record the outputs in table 3. Note that in OrCAD you need to connect (A = B) input to logic 1 (as an indication that previous stages are equal in multi-digit numbers) for correct results while this is not necessary for the hardware. Table 3. Outputs A

B AB

Aaditya Bhetuwal The circuit to compare two 4-bit numbers is,

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Aaditya Bhetuwal And the result of the simulation is,

Now, to fill table.3 from the PSPICE simulation,

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Aaditya Bhetuwal

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Aaditya Bhetuwal

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Aaditya Bhetuwal

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Aaditya Bhetuwal

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So, from the result the given table is,

Outputs A

B AB

1001

0110

0

0

1

1100

1110

1

0

0

0011

0101

1

0

0

0101

0101

0

1

0

Inference: Hence, we use IC 7485 to compare various two 4-bit numbers and found out the output.

Aaditya Bhetuwal

20BDS0406

TASK-f: Magnitude Comparator Using Full adder Aim: To use IC 7483 to build a 4-bit magnitude comparator. Software used: OrCAD (Capture CIS lite)

Question: A magnitude comparator can be constructed by using a subtractor as in Fig 2. And in additional combinational circuit. This is done with a combinational circuit which has 5 inputs S1, S2, S3, S4, and Co, and three outputs X, Y, Z see Fig.4. X = 1 if A = B

Where S = 0000

Y = 1 if A < B

Where Co = 0

Z = 1 if A > B

Where Co = 1

S ≠ 0000

Design and construct this logic circuit with minimum number of gates. Check the comparator action using Part (e). In the Lab verify your OrCAD simulation.

Aaditya Bhetuwal Solution: The functions for X, Y and Z are, Z = (S1 + S2 + S3 + S4)’ Y = C4’ Z = C4 + Z’

So, a 4-bit comparator can be implemented using subtractor like,

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Aaditya Bhetuwal And the result,

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Aaditya Bhetuwal And output for specific combinations are, i)

X = (A = B)

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Aaditya Bhetuwal ii)

Y = (A < B)

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Aaditya Bhetuwal iii)

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Z = (A > B)

Inference: Hence, we used a 4-bit subtractor to implement a 4-bit magnitude comparator.

Aaditya Bhetuwal

20BDS0406

Course: Digital Logic and Design – ELA

Experiment-6: DESIGN WITH MULTIPLEXERS

Name: Aaditya Bhetuwal Regd. No.: 20BDS0406

Aaditya Bhetuwal

20BDS0406

Experiment-6: DESIGN WITH MULTIPLEXERS OBJECTIVE: • To design a combinational circuit and implement it with multiplexers. To use a demultiplexer to implement a multiple output combinational circuit from the same input variables.

APPARATUS: • IC type 7404 HEX inverter • IC type 7408 quad 2-input AND gate • IC type 74151 8x1 multiplexer (1) • IC type 74153 dual 4x1 multiplexer (2) • IC type 7446 BCD-to-Seven-Segment decoder (1) • Resistance network (1) • Seven-Segment Display (1)

Aaditya Bhetuwal

20BDS0406

TASK-a: Parity generator Aim: Using multiplexer design a parity generator. Software used: ORCAD (Capture CIS lite), Proteus

Question: a) Design a parity generator by using a 74151 multiplexer. Parity is an extra bit attached to a code to check that the code has been received correctly. Odd parity bit means that the number of 1’s in the code including the parity bit is an odd number. Fill the output column of the truth table in Table 2 for a 5bit code in which four of the bits (A,B,C,D) represents the information to be sent and fifth bit (x), represents the parity bit. The required parity is an odd parity. The inputs B,C and D correspond to the select inputs of 74151. Complete the truth table in Table 3 by filling in the last column with 0,1,A or A’.

a) Simulate the circuit using LogicWorks, use 74-151 multiplexer and Binary Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Outputs X

Connect data to

Aaditya Bhetuwal

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switches for inputs and Binary Probes for outputs. The 74151 has one output for Y and another inverted output W. Use A and A’ for providing values for inputs 07. The internal values “A, B, C” are used for selection inputs B,C, and D. Simulate the circuit and test each input combination filling in the table shown below. In the Lab connect the circuit and verify the operations. Connect an LED to the multiplexer output so that it represents the parity bit which lights any time when the four bits input have even parity.

Solution:

Let A be the most significant bit, and D be the least significant bit, For both inputs we take A, B and C as select lines and D as the multiplexer functions.

Aaditya Bhetuwal

20BDS0406

a) 4-bit odd parity Firstly, we fill the truth table for odd bit parity checker, Inputs

Outputs Connect data to

A

B

C

D

X

0

0

0

0

1

0

0

0

1

0

0

0

1

0

0

I0 = D’

I1 = D 0

0

1

1

1

0

1

0

0

0 I2 = D

0

1

0

1

1

0

1

1

0

1 I3 = D’

0

1

1

1

0

1

0

0

0

0 I4 = D

1

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

1

1

0

1

0

1

1

1

0

0

1

1

1

1

1

I5 = D’

I6 = D’

I7 = D

Aaditya Bhetuwal

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Now, the circuit for the 4-bit odd parity generator using IC 74151 or 8:1 multiplexer is,

Aaditya Bhetuwal Result

Inference: Hence, using IC 741451, we were able to simulate 4-bit odd parity generator.

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Aaditya Bhetuwal

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b) 4-bit even parity Firstly, we fill the truth table for even bit parity checker, Inputs

Outputs Connect data to

A

B

C

D

X

0

0

0

0

0

0

0

0

1

1

0

0

1

0

1

I0 = D

I1 = D’ 0

0

1

1

0

0

1

0

0

1 I2 = D’

0

1

0

1

0

0

1

1

0

0 I3 = D

0

1

1

1

1

1

0

0

0

1 I4 = D’

1

0

0

1

0

1

0

1

0

0

1

0

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

1

0

1

1

1

1

1

0

I5 = D

I6 = D

I7 = D’

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Now, the circuit for the 4-bit odd parity...