Isolated Continuous Conduction Mode Flyback Using the TPS55340 PDF

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Application Report SLVA559 – January 2013

Isolated Continuous Conduction Mode Flyback Using the TPS55340 Anthony Fagnani ............................................................................................... DCS Industrial DC/DC ABSTRACT Some systems require an auxiliary supply with galvanic isolation between the input power source and output load. This may be a requirement to meet safety ratings such as those defined by UL or the IEC, or to provide a bias supply referenced to a high potential rail. A boost converter with an integrated low-side FET can be used in a flyback topology to make a small solution size isolated power supply. The TPS55340 includes an integrated 40-V, 5-A low-side MOSFET switch for boost, SEPIC or flyback applications. This example design demonstrates the TPS55340 in a flyback topology. An opto-coupler provides feedback to the primary side for highest performance. white

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3 4 5

Contents Design Specifications ....................................................................................................... 2 Calculations and Component Selection .................................................................................. 3 2.1 Switching Frequency (R10) ....................................................................................... 3 2.2 Transformer - Turns Ratio and CCM Duty Cycle .............................................................. 4 2.3 Transformer - Primary Inductance ............................................................................... 4 2.4 Transformer - Ratings and Other Specifications ............................................................... 5 2.5 Resistor-Capacitor-Diode (RCD) Clamp (C4, D2, R1) and RC Snubber (C10, R5) ...................... 6 2.6 Rectifying Diode (D1) .............................................................................................. 7 2.7 Output Capacitor (C5–C6, C8) ................................................................................... 7 2.8 Input Capacitor (C2-C3) ........................................................................................... 8 2.9 IC Power Dissipation .............................................................................................. 8 2.10 Output Voltage Regulation ........................................................................................ 9 2.11 Slow-Start .......................................................................................................... 10 2.12 Small Signal Response .......................................................................................... 11 Evaluation Results ......................................................................................................... 14 Conclusion .................................................................................................................. 14 References ................................................................................................................. 15 List of Figures

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Reference Design Schematic

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CCM Flyback Voltage and Current Waveforms ......................................................................... 3 Opto-Coupler and Feedback Circuitry .................................................................................... 9

4 5

Startup Waveforms ........................................................................................................ 10 Power Stage Small Signal Response ................................................................................... 11

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Compensation Small Signal Response ................................................................................. 12

7 8

Total Loop Small Signal Response ..................................................................................... 13 Efficiency ................................................................................................................... 14

9 10

Load Regulation ........................................................................................................... 14 Isolated Flyback with Bias Winding ..................................................................................... 14

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1

Design Specifications

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List of Tables

1

1

Reference Design Performance Specifications ......................................................................... 2

2

Reference Design Transformer Specifications .......................................................................... 6

Design Specifications TP1

VIN

TP3

GND

T1 12µH

VIN 8 - 24V

J1

C1

+

C2 10µF

1

C3 10µF

J3

C4 0.1µF

R1 1.50k

C9

6

4

TP2 D1

7

C5 0.1µF

C12

J5

NC

SW

PGND

SW

PGND

R5 6.8

12

SS

FREQ

9

330 µF

TP4

7 8

TP6

C17 0.1µF

TP7 R4 49.9

C13

R9 499

R6 4.99k

R8 30.1k

R7 1.00k C14

R11

R12 1

0

R13 1.47k

GND

R3 0

R10 137k

U2 TCMT1107 4 1

TP8

Not Populated

1

VOUT GND

+ C8

C11

0.039µF

SYNC

1

C7

11

PGND U1 TPS55340RTE NC 10

5 6

0.1µF

SYNC

EN

SYNC

4

SW VIN

C6 47µF

4700pF 2kV

FB

3

COMP

2

AGND

VIN

EN OFF

PWPD

17 16 15 14 13 1

J2

5V @ 2.5A

J4 C10 330pF

0.1µF

SYNC GND

5

D2 MURS105T3

TP5

JP1

9

2

R2 0

GND

ON

10

1

3

1 C15

D3 BAT54S

0.1µF U3 TLV431CDBZR

2

C16

R14 10.0k

1 C18 1.0µF

Figure 1. Reference Design Schematic Table 1. Reference Design Performance Specifications Parameter

Conditions

MIN

TYP

MAX

12

24

Units

Input Characteristics Input Voltage Range, VIN

8

Switching Frequency, f SW

350

V kHz

Output Characteristics Output Voltage, VOUT

5

Output Current, IOUT

0

Output Voltage Ripple, VRIPPLE

VIN = 8 V, IOUT = 2.5 A

Conservative Efficiency Estimate, ηEST

VIN = 8 V, IOUT = 2.5 A

100

A mVpp

80%

Load Step, ΔISTEP Transient VOUT Deviation, ΔVOUT Isolation Voltage

V 2.5

1500

1.25

A

200

mV V

Table 1 gives the performance specification of the example design presented. Figure 1 shows the final application schematic. A CCM flyback was selected for this application for improved efficiency, reduced component stress and reduced filter size. A flyback operated in CCM reduces peak currents, RMS currents, and MOSFET turn-off loss. However the main disadvantage of a CCM flyback is the lower control loop bandwidth required to compensate for the presence of a right-half plane zero (RHPZ).

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Isolated Continuous Conduction Mode Flyback Using the TPS55340 Copyright © 2013, Texas Instruments Incorporated

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Q

OFF

ON

OFF

ON VIN+VCLAMP VIN+N×VOUT

VSW

IPRIpeak

iPRI

IIN

iSEC IOUT

Figure 2. CCM Flyback Voltage and Current Waveforms Figure 2 shows the current and voltage waveforms of a CCM flyback during the on-time and off-time of the internal switch (Q). While the switch is turned on, the input voltage is applied across the transformer primary winding energizing the transformer inductance. When Q is turned off, the drain to source voltage flies high due to primary leakage inductance and is clamped at VIN + VCLAMP by an external clamp circuit. The energy stored in the transformer during the on-time of the switch is delivered to the load by the secondary winding during the switch off time.

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Calculations and Component Selection

2.1

Switching Frequency (R10) The first step in the design process is to choose a switching frequency for the power supply. As with any switching regulator, the tradeoff is between higher efficiency and smaller solution size. High switching frequencies allow for lower primary inductance and smaller output capacitors reducing solution size when compared to a converter switching at a lower frequency. However, higher switching frequency increases switching losses hurting the converter’s efficiency and thermal performance. The efficiency of a flyback converter is particularly sensitive to switching frequency. Due to leakage inductance in the transformer, not all energy is transferred from the primary winding to the secondary winding. When the switch is turned off, a large voltage overshoot on the SW pin must be clamped below the drain to source the voltage rating of the internal 40-V MOSFET. The effect of the clamp when the switch turns off is shown in the VSW waveform in Figure 1. The clamping circuit limits VSW to the voltage VIN + VCLAMP. The clamping circuit absorbs the leakage inductance energy during each switching period. Therefore, a higher switching frequency increases the power lost to the primary-side voltage clamp. A switching frequency of 350 kHz near the low end of the TPS55340 operating range is chosen. Designs operating below 300 kHz may experience a collapsed output condition if the switch peak current reaches the overcurrent limit threshold. The collapsed output condition is associated with frequency foldback overload protection. When current limit is exceeded, the device enters frequency fold-back and the switching frequency reduces to ¼ the nominal value set by RFREQ. At switching frequencies less than 75 kHz, the peak current limit threshold of the device also decreases. The output voltage must return to regulation before the switching frequency returns to the pre-set value. However, with the reduced current

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Calculations and Component Selection

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limit threshold, the output voltage will remain below the regulation level until the load current is reduced. The converter can be restarted from this overload condition by cycling the input power, cycling the EN pin or removing the output load. The resistance required to set the switching frequency is calculated with Equation 1 from the product data sheet. For a 350-kHz switching frequency, the calculated resistance is 137.8 kΩ. The nearest standard value of 137 kΩ is used.

RFREQ (k: )

2.2

57500u fSW (kHz)1.03

57500u 350(kHz)1.03

137.8k:

(1)

Transformer - Turns Ratio and CCM Duty Cycle When designing a flyback the most important component is the transformer. Typically the first specification selected is the turns ratio. The turns ratio is chosen to limit the duty cycle to a maximum of 50% (Dlim). There are two reasons to do this. First, it reduces stress on the rectifying diode and output capacitors. Second, it avoids the possibility of sub-harmonic oscillation inherent to current mode control. The TPS55340 provides internal slope compensation and can be stable with duty cycles greater than 50%. The maximum primary to secondary turns ratio (Np2s) is calculated with Equation 2. This includes an estimated 0.5 V drop of the rectifying diode (VD). VIN minu Dlim 8V u 0.5 Np2s 1.45  VOUT  VD u 1  Dlim  5V  0.5V u 1  0.5 (2) The calculated maximum Np2s is 1.45. The transformer used in the example has 12 primary turns and 10 secondary turns giving an Np2s of 1.2. After selecting the turn’s ratio it should be verified the 40-V internal MOSFET of the TPS55340 is sufficient for the voltage stress in the design. In a flyback topology the drainto-source voltage across the low-side MOSFET is the input voltage plus the output voltage reflected to the transformer primary. At least a 20% margin is recommended to account for voltage overshoot due to the leakage inductance of the transformer and any ringing caused by PCB parasitics. The voltage stress on the MOSFET is calculated with Equation 3 where the 0.8 factor in the denominator provides the 20% voltage margin. With the selected turns ratio the estimated voltage stress on the MOSFET is 38.2 V.

VFET

VINmax  VOUT  VD  uNp2s 0.8

24V  5V  0.5V  u1.2 0.8

38.2V (3)

After selecting the turns ratio, the duty cycle in CCM can be estimated with Equation 4. This includes the forward voltage drop of the rectifying diode. With the minimum input voltage (VIN min), Dmax equals 45.2% and with the maximum input voltage (VINmax), Dmin equals 21.6%. DCCM

2.3

 VOUT  VD  u Np2s VIN   VOUT  VD  u Np2s

5V  0.5V  u1.2 8V  5V  0.5V u 1.2

0.452 (4)

Transformer - Primary Inductance The desired primary inductance is the next important specification to select for the transformer. The two main concerns when specifying the inductance are the current ripple and the RHPZ. A higher inductance reduces the current ripple which can lower EMI and noise. However, larger inductance increases physical size and limits the bandwidth of the loop due to a lower frequency RHPZ. On the other hand, a lower inductance increases the current ripple, increasing EMI, noise and RMS currents while supporting a smaller solution size and faster control loop bandwidth. One method to choose the inductance is to limit the current ripple to a percentage of the average current through the primary winding during the on time of the switch. A fair tradeoff between size and efficiency is achieved with a percent ripple (RIP%) between 60% and 90%. The average primary current is calculated using Equation 5. The recommended inductance is then calculated with Equation 6. Both equations are evaluated at the maximum input voltage when the peak to peak current ripple is greatest. VOUT u IOUT 5V u 2.5A IRIPPLE RIP% u 0.6 u 1.45A VIN maxu Dmin 24V u 0.216 (5) LPRI

4

VIN maxu Dmin IRIPPLE u fSW

24V u 0.216 1.45A u350kHz

10.2P H

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(6)

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With a RIP% of 60%, the target IRIPPLE is 1.45 A and the inductance is 10.2 µH. The selected primary inductance is 12 µH. Using this inductance with Equation 5 and Equation 6 produces a current ripple of 1.23 A. The RHPZ frequency is estimated with Equation 7 ignoring the resistance of the windings. This is evaluated when the frequency of the RHPZ is lowest, at the minimum input voltage and the maximum output current. For a stable design it is recommended to limit the loop bandwidth (fBW) at the minimum input voltage to 1/3 the RHPZ frequency. The RHPZ is calculated at 25.4 kHz and the maximum recommended loop bandwidth is 8.5 kHz. VOUT 2 5V 2 u  1  Dmax u  1  0.452 IOUT 2.5A fRHPZ 25.4kHz L 12 PH 2 S u PRI 2 u Dmax 2S u 0.452 u 1.2 2 Np2s (7) With the primary inductance selected the maximum output current is estimated based on the current ripple and estimated efficiency using Equation 8. The maximum output current is estimated at 2.79 A. IOUT max

I RIPPLE · VIN minu Dmaxu KEST § u ¨ ILIM min 2 ¹¸ VOUT ©

1.23A · 8V u 0.452 u 80% § ¨ 5.25A  2 ¸ u 5V © ¹

2.79A (8)

In a flyback topology the supply enters DCM when all power stored in the transformer during the on-time of the switch is transferred to the load before the end of the switching period, leaving no residual energy in the transformer. The current at which CCM operation begins is estimated with Equation 9. This estimation is typically high because efficiency is not included. The critical current to enter DCM is estimated at 310 mA with an 8-V input voltage and 640 mA with a 24-V input voltage. Lastly the DCM duty cycle is estimated with Equation 10. This shows the dependence on the switching frequency, primary inductance and output current. IOUT crit

DDCM

2.4

VIN2 u D CCM2 2 u L PRI u f SW u VOUT

8V 2 u 0.4522 2 u 12PH u 350kHz u 5V

2 uIOUT u fSW uLPRI u  VOUT  VD

310mA (9)



2

VIN min

(10)

Transformer - Ratings and Other Specifications After selecting the inductance and turns ratio some other necessary ratings for the transformer must be specified. The most important is to minimize the leakage inductance. As mentioned previously, leakage inductance related to imperfect coupling between the primary and secondary windings causes power loss in the primary switch clamp circuit. A good rule is to target the leakage inductance below 2% the selected primary inductance. The saturation current rating of the transformer must also be specified. Magnetics vendors typically describe this as the current in primary winding when the primary inductance decreases to 20% of the nominal value. Conservative designs will use the 6.6-A typical peak current limit of the TPS55340 as the saturation current. The minimum recommended saturation current rating is 20% higher than the calculated peak current under full load. Equation 11 estimates the peak current. With the selected primary inductance in this design, the peak current is 4.75 A and the minimum recommended saturation current rating is 5.94 A. VOUT u IOUT I 5V u 2.5A 1.23A  RIPPLE  IPRI peak 4.75A VIN minu Dmaxu KEST 2 8V u 0.452u 80% 2 (11) The DC resistance (DCR) of the windings should also be minimized to reduce conduction power losses. The RMS current in the primary winding is estimated with Equation 12, the RMS current in the secondary winding with Equation 13 and the conduction power loss with Equation 14. In the example using VIN of 8 V, the primary RMS current is 2.92 A and the secondary RMS current is 1.9 A. IPRI rms

2 2· §§ V uI · I Du ¨ ¨ OUT OUT ¸  RIPPLE ¸ VIN u D ¹ 3 ¨ ¸ ©© ¹

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§ § 5V u 2.5A · 2 0.86A 2 · ¸ 0.452u ¨ ¨  ¨ 8V u 0.452 ¸¹ ¸ 3 ©© ¹

2.92A<...