Lab 24 - I DONT REMEMBER PDF

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Summary

I DONT REMEMBER...

Description

Lab

24

Parameterized Counters Name _______________________________________

Objectives

Class ______________

Date

Upon completion of this laboratory exercise, you should be able to: • Create a block diagram file in Quartus II that contains a counter from the Altera Library of Parameterized Modules (LPM). • Customize the LPM counter to select required ports and parameters of the correct active level and value. • Create on LPM counter in VHDL. • Create Quartus II simulation files to verify the operation of the circuits designed for this laboratory exercise. • Download the counter and shift register designs to a CPLD test board and demonstrate their operation.

Reference

Equipment Required

Dueck, Robert K., Digital Design with CPLD Applications and VHDL, 2/e Chapter 9: Counters and Shift Registers LPM Counters Altera, LPM Quick-Reference Guide (Available on the CD accompanying Digital Design with CPLD Applications and VHDL, 2/e in the file lpm.pdf CPLD Trainer: DeVry eSOC board with Parallel Port cable, or Altera UP-2 circuit board with ByteBlaster Download cable, or RSR PLDT-2 circuit board with Straight-Through Parallel Port Cable, or equivalent CPLD trainer board with Altera EPM7128S CPLD Quartus II Web Edition software AC adapter, minimum output: 7 VDC, 250 mA DC Anti-static wrist strap #22 solid-core wire Wire strippers

Experimental Notes

•

Altera offers a library of components that can be used in Quartus II as part of a VHDL or graphic design file. These LPM (Library of Parameterized Modules) components can be easily modified to create designs of any required size. For example, a parameter called LPM_WIDTH can be set to a given value to make a counter or shift register from 1 to 256 bits wide, subject to the number of logic cells available in a given CPLD. A list of LPM components and a summary of their functions are given in the document lpm.pdf, available on the CD that accompanies Digital Design with CPLD Applications and VHDL, 2/e, in the folder called Student_Lab_Files. We will examine the use of a parameterized counter (lpm_counter). A parameterized shift register will be examined in another lab.

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Lab 24

An LPM module is specified by ports and parameters. A port is an input or output of the device, with a function such as clock, clear, or load. A parameter is a property of the block, such as LPM_WIDTH, a parameter that specifies how many bits its parallel input or output has. Port names are written in lower case; parameter names are in upper case, in the form LPM_parameter. Some ports and parameters, such as clock and LPM_WIDTH, must be used in all instances of lpm_counter. Others, such as aclr and LPM_DIRECTION, are optional. Figure 24.1 shows the symbol for the lpm_counter component with its complete set of ports and parameters. The function of each port and permissible values of the parameters are listed in the Help for each component, accessible from the Properties dialog box or the Quartus II Help menu. Table 9.13 in Digital Design with CPLD Applications and VHDL 2/e lists the required ports and parameters for various functions of lpm_counter. When using an LPM component in a VHDL file, the component requires a library reference at the beginning of the file: LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL;

Figure 24.1 Available Port and Parameters for an LPM Counter

197

Parameterized Counters

Procedure

•

LPM Counter (Block Diagram File) 1. Use the Quartus II Block Editor to create an LPM counter with the ports and parameters shown in Figure 24.2. Save the file as drive:\qdesigns\labs\lab24\ct8lpm\ct8lpm.gdf and use it to create a project in Quartus II. Compile the project.

Figure 24.2 8-Bit LPM Counter

2. Create a simulation of the counter that tests all of the functions according to the following checklist: ____ Tests one full cycle of the count sequence (requires a modified end time) ____ Shows that load is really synchronous ____ Shows the difference between count enable and clock enable functions ____ Tests asynchronous reset Show the simulation to your instructor. Instructor’s Initials _________

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Lab 24

3. Create a test circuit, shown in Figure 24.3 (RSR PLDT-2) or 24.4 (Altera UP-2 or DeVry eSOC). Assign pin numbers as shown in Table 24.1 (PLDT-2 or UP-2) or in Table 24.2 on page 173 (DeVry eSOC). Compile the file and download it to the CPLD test board. Table 24.1 EPM712BSLC84-7 Pin Assignments (UP-2 or PLDT-2) Pushbuttons and Clock Function pb_in

Pin 11

clk

83

Function Reset

Pin 1

DIP Switches Function p[7]

Pin 34

Function

Pin 28

p[6]

33

29

p[5]

36

30

p[4]

35

31

p[3]

37

p[2]

40

clock_en

55

p[1]

39

count_en

56

p[0]

41

load

54

57

LED Outputs Function q[7]

Pin 44

Function unused[7]

Pin 80

q[6]

45

unused[6]

81

q[5]

46

unused[5]

4

q[4]

48

unused[4]

5

q[3]

49

unused[3]

6

q[2]

50

unused[2]

8

q[1]

51

unused[1]

9

q[0]

52

unused[0]

10

4. Test the functions of the LPM counter, including count, load, and reset. Show how count enable differs from clock enable. Demonstrate the circuit to your instructor. Instructor’s Initials _________

LPM Counter (VHDL) 1. Refer to Altera’s LPM Quick Reference or Quartus II Help to find the functions of the following ports and parameters for lpm_counter: updown, sset, LPM_MODULUS, LPM_DIRECTION, and LPM_SVALUE.

Parameterized Counters

Figure 24.3 LPM Counter Test Circuit (RSR PLDT-2)

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200

Figure 24.4 LPM Counter Test Circuit (Altera UP-2 and DeVry eSOC)

Lab 24

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Parameterized Counters

Table 24.2 EPM7128LC84-7 Pin Assignments DeVry eSOC Board Pushbuttons Function PB_IN Reset

Pin 70 73

Function

Pin

DIP Switches Function p[7]

Pin 50

Function

Pin 60

p[6]

51

61

p[5]

52

63

p[4]

54

64

p[3]

55

65

p[2]

56

clock_en

67

p[1]

57

count_en

68

p[0]

58

load

69

LED Outputs Function q[7]

Pin 4

Function unused[7]

Pin 16

q[6]

5

unused[6]

17

q[5]

8

unused[5]

18

q[4]

9

unused[4]

20

q[3]

10

unused[3]

21

q[2]

11

unused[2]

22

q[1]

12

unused[1]

24

q[0]

15

unused[0]

25

Special Function: Pin 83 (CLK; hardwired)

2. Write a VHDL file that uses an the smallest possible LPM counter to perform the following functions: a. count up or down, depending on the state of an input called direction; b. synchronously set the counter output value to 2AH (4210) with an active-LOW input called setn; c. set the counter modulus to 5010. 3. Create a simulation file that demonstrates these functions. Show the simulation waveforms to your instructor. Instructor’s Initials _________

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Lab 24

4. Add a debouncer to your design as a VHDL component. Do not use the Quartus II Block Editor. Remember to invert your counter outputs if you are using the Altera UP-2 or DeVry eSOC board so that the LEDs on the board will sequence correctly. Assign pins as needed. Compile the design and download it to the CPLD test board. Demonstrate the operation of the counter to your instructor. Instructor’s Initials _________...