LC-3 - desc PDF

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Description

LC-3 Instruction set architecture (ISA) It is an interface between what software commands and how hardware handles it. ISA specifies 1. Memory organization 2. Register set 3. Instruction set (which includes) a) Opcodes b) Data types c) Addressing modes 1. Memory:   

The memory space (address space) in LC-3 is 216=65535 locations So the addressability is 16 bits. 16 bits are referred to as “word” and we say LC-3 is word addressable i.e. 216 by 16 bit memory.

2.Register set :     

It is the temporary storage available in processing unit. It is the memory that can be accessible in one machine cycle. Comprised of 8 registers called “general purpose registers”(GPRs). Each register is capable of storing a word. These registers are addressable with 3 bit-pattern which uniquely can identify a register. We call these registers as R0, R1….R7.

3.Instruction set: a) Opcodes:  This uniquely identifies each instruction.  It uses 4-bit representation.  So there can be 16 different opcodes.  But LC-3 has 15 different opcodes for various instructions.( 1011 is unspecified)  This is specified by [15:12] bits in an instruction. Eg: ADD opcode is 0001 NOT opcode is 1001 b) Datatypes: 2’s complement binary representation is used. Information representation is such that operations can be performed on them.

c) Addressing modes: It is the mechanism to locate the operands. Source operands can be located in 1) Memory (LDR) 2) Register (ADD) 3) part of instruction (literal or immediate)

Conditional codes:  These codes are significant in case of branch instructions  LC-3 has three one bit registers with value 0 or 1  They are called N, Z and P  They are set to 0 or 1 each time a value is written in a GPR.  If negative value is written in GPR: N is set to 1 Z and P are set to 0.

INSTRUCTONS They are of three types a) Operate instructions b) Data movement instructions c) Control instructions

a) Operate instructions: They are for processing information. LC-3 has three operate instructions: NOT (unary operation) opcode – 1001 ADD (binary operation) opcode – 0001 AND (binary operation) opcode - 0101

NOT: It requires one source operand and one destination operand. Both source and destination belong to register set. Syntax

1001

Bit number 15

DR SR 111111

12 11

9 8

6 5

0

DR=Destination Register SR=Source Register Eg: 1001 110 011 111111 NOT

R6

R3

Contents of R3 are bit-wise NOTed and result is stored in R6.

When this is written old information in R6 is lost.

ADD and AND: They require two source operands (binary operations) and a destination which is a register. However one of the source should be a register. OPCODE DR SR1 0 00 SR2 15

12 11 9 8

6 5

4 3

2

0

[11:9] Destination register (DR) [8:6] Source Register1 Second operand can be from register set or can be a part of instruction. Bit [5] is essentially used for this. If Bit [5] =0 the second source is also a register and is specified in [2:0] and Bit [4:3] remains zero. If Bit [5] =1 the second source is obtained by sign extending bits [4:0] to 16 bits. OPCODE DR SR1 1 Immediate 15

12 11 9 8

6

5

4

0

Eg: OPCODE 010 010 1 11001 Now [4:0] is 11001 So the sign extension becomes 11111111111 11001 (the first eleven 1’s are produced due to sign extension) Eg2: Consider 0101 101 101 1 00000 The opcode indicates this is AND instruction the destination register is R5 ( 101 ) the first source is also R5 ( 101 ) Since the Bit 5 is 1;This indicates the second source is immediate number which is 0. This instruction ANDs contents of R5 with 0 and stores it in R5. So the contents of R5 are set to 0 after the execution of this instruction.

Eg3:Consider 0001 101 101 1 00001 The OPCODE indicates it is ADD instruction. So this adds one to the contents of R5 (increments R5)

DataMovement Instructions:-

They can be of two types a) Memory to Register (load) b) Register to Memory (store) There are 7 datamovement instructions in LC-3 LD, LDI, LDR, LEA, ST, STI and STR Format for these instructions is OPCODE DR or SR Address generation bits 15

12

11

9

8

0

Load essentially means moving the contents of memory from a location computed from bits [8:0] into a destination register specified by [11:9] Store is moving contents of source register specified by [11:9] into a memory location whose address is computed using bits[8:0] Note: -The contents of source are unaltered and contents of destination are overwritten. The memory location is identified by various addressing modes available in LC-3. They are 1) PC – Relative mode 2) Indirect mode 3) Base + offset mode

PC Relative mode: LD and ST use this type of addressing mode. LD or ST

DR or SR Offset

Address is computed by adding the incremented program counter(PC) to the sign extended bits [8:0]

Eg: 0010 101 101000010 LD

DR =R5

x4011 IN IR

PC is incremented to x4012 Evaluating the address → 0100 0000 0001 0010 (incremented PC) + 1111 1111 0100 0010 (sign extended offset) ______________________ x3F54 {In hexa-decimal notation} Step 1 Increment PC + sign extended IR[8:0]

Load into MAR Step 2 Access memory and load the contents into MDR Step 3 Load the contents of MDR into destination register Note:The procedure is same for ST operation except that the data movement is in opposite side. Indirect Mode: The instruction which use this addressing mode are LDI – 1010 STI – 1011 Address is computed in the same way as in LD or ST but in this case it contains the address of the operand to be stored or loaded. Step 1: Increment PC + sign extended IR[8:0] Load into MAR Step 2 Access memory and load the contents into MDR Step 3 Address is loaded in MAR Step 4 Access memory and load contents in MDR register Step 5 Contents of MDR are loaded in DR Base + Offset mode: The instructions that use this mode are LDR – 0110 STR – 0111 LDR or STR DR or SR Base Offset Contents of base + sign extended offset are loaded or stored in DR or SR Immediate mode :Memory is not accessible in this mode The instruction that uses this is

LEA(load effective address) – 1110 1110 Register Immediate number PC increment value + sign extended [8:0]

is loaded into register specified by [11:9]

CONTROL INSTRUCTIONS:Conditional codes:Three one bit registers N,Z and P are present along with the register set ADD, NOT, AND, LD, LDI, LDR, and LEA –these all instructions write into GPRs Whenever the above instructions are being executed one of these one-bit registers is set. The execution of condition branch instructions depend on the values set in these registers. Conditional Branch: BR

0000 N Z P PC offset 9 The condition codes specified by the state of the bits [11:9] are tested. If bit [11] is set N is tested and if bit [11] is clear N is not tested Similarly if bit [10] is set Z is tested. If any of the condition codes tested is set, the program branches to the location specified by adding the sign extended PC offset9 field to the incremented PC. Eg: BRzp BR

LOOP - Branch to LOOP if the last result was zero or positive. NEXT - Unconditionally branch to NEXT (BRnzp also does the same operation)

Example:Initially the contents of PC is x30F6 i.e. the first instruction to be executed is located in x30F6. x30F6

1110 001 111111101 LEA

R1

R1 ←x30F7 + SEXT [8:0] = x30F4 Step 1 R1 contains x30F4 and PC is incremented to x30F7 x30F7

0001 010 001 1 01110 ADD

R2

R1

imm Mode

R2 ← R1 + SEXT [4:0] =x30F4 + SEXT[4:0] = x3102

Step 2 R2 contains x3102 and PC is incremented to x30F8 x30F8

0011 010 111111011 ST

R2

M[x30F9 + SEXT[8:0] ] ← R2 =x30F4 Step 3 Memory location x30F4 contains content of R2 which is x3102 PC is incremented to x30F9 x30F9 0101 010 010 1 00000 AND

R2

R2

R2←0 Step 4 Cleared R2 and PC incremented to x30FA 0001 010 010 1 00101

x30FA

ADD

R2

R2

imm Mode

R2←R2 + SEXT[4:0] Step 5 R2 contains 5 PC incremented to x30FB x30FB

0111 010 001 001110 STR

SR

M[ R1 + SEXT[5:0] ] ← R2 M[x30F4 + SEXT[5:0] ] =M[x3102] ← 5

x30FC

0010 011 1111101111 LDI

R3

R3← M [ M[x30FD] + SEXT [8:0] ] =x30F4 R3←5...