MID 2018, questions and answers PDF

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USMAN INSTITUTE OF TECHNOLOGY DEPARTMENT OF COMPUTER SCIENCE MID SEMESTER EXAMINATIONS – FALL 2018

CS212 COMPUTER ARCHITECTURE AND ORGANIZATION Time Allowed:

1

1 2 Hours

Max Marks: 20

Instructions:    

Read all questions carefully first and then ask for clarifications. Question paper related queries will not be entertained after 30 minutes after start of paper. Do not write anything on question paper unless until specifically asked for. Please fill the required information and return the question paper along with the answer script.

Name ____________________________________

Roll No.________________________________________

QUESTION NO: 1) Draw a detailed Von Neumann architecture and explain function of registers in it.

Marks (04)

MAR

Memory Address Register

Holds the memory location of data that needs to be accessed

MDR

Memory Data Register

Holds data that is being transferred to or from memory

AC

Accumulator

Where intermediate arithmetic and logic results are stored

PC

Program Counter

Contains the address of the next instruction to be executed

CIR

Current Instruction Register

Contains the current instruction during processing

QUESTION NO: 2) Marks (04) In a computer system PCI bus is used to connect peripheral devices to the processor (system bus) bus. Consider a bus transaction in which the processor reads for 32-bits from the memory. Explain the read operation on the PCI bus between memory and processor with the help of a timing diagram.

Figure 2:

Timing diagram for a typical read transaction. Clock1: The bus is idle and most signals are tri-stated. The master for the upcoming transaction has received its GNT# and detected that the bus is idle so it drives FRAME# high initially. Clock 2: Address Phase: The master drives FRAME# low and places a target address on the AD bus and a bus command on the C/BE# bus. All targets latch the address and command on the rising edge of clock 2. Clock 3: The master asserts the appropriate lines of the C/BE# (byte enable) bus and also asserts IRDY# to indicate that it is ready to accept read data from the target. The target that recognizes its address on the AD bus asserts DEVSEL# to acknowledge its selection. This is also a turnaround cycle: In a read transaction, the master drives the AD lines during the address phase and the target drives it during the data phases.

Whenever more than one device can drive a PCI bus line, the specification requires a one-clock-cycle turnaround, during which neither device is driving the line, to avoid possible contention that could result in noise spikes and unnecessary power consumption. Turnaround cycles are identified in the timing diagrams by the two circular arrows chasing each other. Clock 4: The target places data on the AD bus and asserts TRDY#. The master latches the data on the rising edge of clock 4. Data transfer takes place on any clock cycle during which both IRDY# And TRDY# are asserted. Clock 5: The target deasserts TRDY# indicating that the next data element is not ready to transfer. Nevertheless, the target is required to continue driving the AD bus to prevent it from floating. This is a wait cycle. Clock 6: The target has placed the next data item on the AD bus and asserted TRDY#. Both IRDY# and TRDY# are asserted so the master latches the data bus. Clock 7: The master has deasserted IRDY# indicating that it is not ready for the next data element. This is another wait cycle. Clock 8: The master has reasserted IRDY# and deasserted FRAME# to indicate that this is the last data transfer. In response the target deasserts AD, TRDY# and DEVSEL#. The master deasserts C/BE# and IRDY#. This is a master-initiated termination. The target may also terminate a transaction as we’ll see later. QUESTION NO: 3) Marks (04) a) Mention the advantages of RISC over CISC. b) What is the difference between DRAM and SRAM in terms of characteristics such as speed, size, and cost?

COMPARISON

Speed

SRAM

Faster

DRAM

Slower

COMPARISON

SRAM

DRAM

Size

Small

Large

Cost

Expensive

Cheap

Used in

Cache memory

Main memory

Density

Less dense

Highly dense

Construction

Complex and uses

Simple and uses capacitors

transistors and latches.

and very few transistors.

6 transistors

Only one transistor.

Not present

Present hence require power

Single block of memory requires Charge leakage property Power consumption

refresh circuitry Low

High

QUESTION NO: 4) a) How many 128*8 RAM chips are needed to provide a memory capacity of 2048 bytes?

     

16 2048By t es=2048x8bi t s=16384bi t s 128x8=1024bi t s Noof128x8chi ps=Requi r edTot alMemor y( 16384) / 1024=16 or Noof128x8chi ps=Requi r edTot alMemor y( 2048) / 128=16

b) Explain the phases of an instruction cycle with necessary control functions and micro operations.

Marks (04)

Summary: Execution of a program consists of sequential execution of instructions. Each instruction is executed during an instruction cycle made up of shorter subcycles(example – fetch, indirect, execute, interrupt). The performance of each subcycle involves one or more shorter operations, that is, micro-operations.

The circuits used in the CPU during the cycle are:      

Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next... Memory Address Register (MAR) - the address in main memory that is currently being read or written Memory Buffer Register (MBR) - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory Current Instruction register (CIR) - a temporary holding ground for the instruction that has just been fetched from memory Control Unit (CU) - decodes the program instruction in the CIR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources Arithmetic logic unit (ALU) - performs mathematical and logical operations

QUESTION NO: 5) Marks (04) Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache that uses a 64-byte line size.

i.

ii.

Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag.

i. Address format: Tag = 20 bits; Line = 6 bits; Word = 6 bits. Number of addressable units = 232bytes; number of blocks in main memory = 226; Number of lines in cache = 26 = 64; size of tag = 20 bits. ii. Address format: Tag = 26 bits; Word = 6 bits. Number of addressable units = 232 bytes; number of blocks in main memory = 226; Number of lines in cache = undetermined; size of tag = 26 bits....