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Simulation Activity #NMOS and PMOS AmplifiersName: Trisia Ann M. Luna C/Y/S: BSECE/3 rd year/STEE314 Date Completed: September 13, 2021Objective:To implement the schematics of an N and P-Channel Metal Oxide Transistors (MOS) as a static switch and verify their characteristics thru simulation using L...

Description

Simulation Activity #2 NMOS and PMOS Amplifiers

Name: Trisia Ann M. Luna

C/Y/S: BSECE/3rd year/STEE314

Date Completed: September 13, 2021

Objective: To implement the schematics of an N and P-Channel Metal Oxide Transistors (MOS) as a static switch and verify their characteristics thru simulation using LTSpice software. Introduction: The strength of a signal is measured by how closely it approximates an ideal voltage source. In general, the stronger a signal, the more current it can source or sink. The power supplies, or rails, (V DD and GND) are the source of the strongest 1s and 0s. An NMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a strong 0. However, the NMOS transistor is imperfect at passing a 1. The high voltage level is somewhat less than VDD. We say it passes a degraded or weak 1. This is mainly due to a voltage drop caused by a practical MOS parameter known as the threshold voltage, VTH. 1. Using the LTSpice software, create and simulate the DC Operating Point of the NMOS switch circuit in Figure 1, with the given test conditions from Table 1. Note: make sure to use the transistor model BSIM3v31.txt for all simulations. Complete the information required from the same table. Provide your analysis and observation.

Figure 1. NMOS as a switch

Vg

Vi n

Vout

0

0

OV

0

5V

0.343337V

5V

0

8.70845e-

IG 0 A 0 A 0

ID

IS

PVG

PVIN

0A

0A

0W

0W

-4.283e-0.20A

5.36334e-012A

0W

-26.816685pW

0A

0A

0W

0W

STEE314 – Logic Circuits and Switching Theory Darwin D. Mañaga, Meng-ECE, PECE, ACPE

5V

5V

017V 4.63222V

A 0 A

-2.43864e-015A

9.65466e-012A

0W

-48.261122pW

Table 1

Observation and Analysis: Vout rose because both Vg and Vin increased/gained voltage, as seen by the results of the previous simulations. Furthermore, the NMOS appears to be an ON switch only when Vg and Vin are equal to or greater than 5. PVIN also demonstrates that there is a negative difference between Vin 0 and Vin 5V. PVG, on the other hand, remains 0W throughout all simulations, as does IG. When Vin is 0 or 5, ID and IS show both positive and negative disparities. 2. Next, simulate the PMOS switch circuit as shown in Figure 2. with the given test conditions from Table 1. Complete the information required from the same table. Provide your analysis and observation.

Figure 2. PMOS as a switch

Vg 0 0 5V 5V

Vin 0 5V 0 5V

Vout 0.606688V 5V 3.6V 3.8041V

IG 0A 0A 0A 0A

ID 4.148e-018A 5.04154e-018A 2.52944e-018A -3.81395e-019A

IS -6.61332e-012A 2.51969A -3.61e-012A 2.51953A

PVin 0W -12.598469W 0W 0W

PV1 -23.807924pW 9.0708976W -12.996001pW 9.0703063W

Table 2

Observation and Analysis: The results of the PMOS reveal a variation in Vout based on the Vg and Vin setup, as shown in Table 2. The V1 has the most impact on the last two configs in the Vout results. Also, we can see a clear Vout of 5V in config 2, which is the same as the input Vin, implying that the gate Vg functions as a switch when it is 0 and as an off switch when it reaches 5V. 3. For the NMOS and PMOS switch circuits, perform a DC sweep simulation of Vin from 0 to 3.6V, with a step size of 100mV when VG is 0 and 1. Provide your analysis and observation. STEE314 – Logic Circuits and Switching Theory Darwin D. Mañaga, Meng-ECE, PECE, ACPE

Observation and Analysis: In PMOS, I discovered that the initial voltage output increases as Vg increases, and at some point, the graphs of Vout and Vin will meet, and both graphs will increase with equal values. Based on this, I deduce that the circuit turns on and stays on at the intersection of the two graphs, which will be defined by the value of Vg. In NMOS, the graph of Vout climbs with the same slope as Vin until a particular voltage value is reached, at which point the slope of Vout becomes zero and the value of Vout becomes constant. I've also noticed that as the value of Vg rises, this point rises as well. Because the value of VG is equal to or greater than 0, I deduce that the circuit is ON, but the increase in output voltage is limited by the value of VG. As the value of VG rises, so does the point at which Vout remains constant. 4. Repeat measurement # 3 with load capacitance of 100fF, 500nF and 1uF. Provide your analysis and observation. Observation and Analysis: 

According to my observations, there are no major changes between the three configurations in terms of NMOS and PMOS findings. When the load capacitance is increased, the NMOS produces finer results than the PMOS. When the load capacitance is raised, the PMOS and NMOS provide quite different outcomes.

5. For the switch circuit in Figure 3, repeat measurements 3 and 4. Provide your analysis and observation.

Observation and Analysis: 

Because Vgn = 0 and Vgp = 1, the circuit operates as a PMOS switch. However, because Vgn = 1 and Vgp = 0 in the NMOS circuit, there is a moment after the limit is reached where the increase in value STEE314 – Logic Circuits and Switching Theory Darwin D. Mañaga, Meng-ECE, PECE, ACPE

continues. Because both Vgn and Vgp are zero or one, the graph is a mix of NMOS and PMOS graphs. Because the changes in the graph are minor, the changes in capacitance are difficult to notice, but the graph smooths out as the capacitance lowers, according to my observations. As the capacitance grows, the changes in slop become more distinct. 6. Repeat measurement # 3 for different combinations of MOS width (w) as depicted on table 3. Provide your analysis and observation. Wn Wp 0.8 µm 3.2 µm 0.8 µm 1.6 µm 0.8 µm 0.8 µm Table 3

Summary of Observations: 

The distinctions between NMOS and PMOS have been observed as a summary for this Laboratory Activity. The effect of Vg on the resulting Vout in the two configurations has been demonstrated. Furthermore, how these two MOSFET designs contribute to the operation of a CMOS has been demonstrated in this activity.

Note: You could visit LTwiki-Wiki for LTspice for more information in using the LTSpice tool.

STEE314 – Logic Circuits and Switching Theory Darwin D. Mañaga, Meng-ECE, PECE, ACPE...