Tutorial 2 (e) Floating-Point Representation PDF

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COMPUTER ORGANIZATION AND ARCHITECTURE (SECR2033) TUTORIAL 1&2 task Chapter 2 Floating-Point Representation Due date – Sunday (15/11/20) – 10pm Fixed-Point Representation − This representation has fixed number of bits for integer part and for fractional part. For example, if given fixed-point representation is IIII.FFFF, then you can store minimum value is 0000.0001 and maximum value is 9999.9999. There are three parts of a fixed-point number representation: the sign field, integer field, and fractional field.

Example −Assume number is using 32-bit format which reserve 1 bit for the sign, 15 bits for the integer part and 16 bits for the fractional part. Then, -43.625 is represented as following:

Where, 0 is used to represent + and 1 is used to represent. 000000000101011 is 15 bit binary value for decimal 43 and 1010000000000000 is 16 bit binary value for fractional 0.625. Question1 a. Represent -53.255 using 32-bit format which reserve 1 bit for the sign, 15 bits for the integer part and 16 bits for the fractional part. b. Represent 25.123 using 32-bit format which reserve 1 bit for the sign, 15 bits for the integer part and 16 bits for the fractional part. c. Represent -19.678 using 32-bit format which reserve 1 bit for the sign, 15 bits for the integer part and 16 bits for the fractional part. d. Refer to the URL given as extra material, translate the decimal number of 46.243 e. Refer to the URL given above, translate the binary number of 11010.1101 f.

Change 253200 into mantissa and exponent

g. Change 5631000 into mantissa and exponent

Question 2 a. Convert 12.2510 using IEEE 754 single precision floating point conversion steps b. Convert 765.04 using IEEE 754 single precision floating point conversion steps c. Convert -0.75d using IEEE 754 

single precision floating point.



double precision floating point.

Question 3 d. What decimal number is represented by this single precision float? Sign (1 bit) 1

Exponent(8 10011001

Significand(23 bit) 01011000000000000000000

e. What decimal number is represented by this single precision float? Sign (1 bit) 0

Exponent(8 10000110

Significand(23 bit) 10111000000000000000000

Question 4 Study the Booth’s algorithm for two complements multiplication steps below. 1. 2. 3. 4. 5. 6.

Multiplier and multiplicand are placed in the Q and M register respectively. Result for this will be stored in the AC and Q registers. Initially, AC and Q-1 register will be 0. Multiplication of a number is done in a cycle A 1-bit register Q-1 is placed right of the least significant bit Q0 of the register Q. In each of the cycle, Q0 and Q-1 bits will be checked. i. If Q0 and Q-1 are 11 or 00 then the bits of AC, Q and Q-1 are shifted to the right by 1 bit. ii. If the value is shown 01 then multiplicand is added to AC. After addition, AC, Q 0, Q1 register are shifted to the right by 1 bit. iii. If the value is shown 10 then multiplicand is subtracted from AC. After subtraction AC, Q0, Q-1 register is shifted to the right by 1 bit.

Example 1: Let us multiply (-6) and (2) using Booth’s algorithm. M Q Solution: (6)10 = (0110)2 As it is given multiplicand, M= (-6)10 =2 complement of 0110 = 1010 Multiplier, Q= (2)10 = 0010 Q3

Q2

Q1

Q0

Q-1

0

0

1

0

0

Steps

AC

Q

Q-1

Initial

0000

0010

0

initial

Q0,Q-1 from initial = 0 0

1

0000

0001

0

shift

AC, Q and Q-1 are shifted to the right by 1 bit.

2

0110

0001

0

AC=AC-M AC = (AC step1 –M) 1 1 0

1 0 1

0 1 1

0 0 0

3

0011

0000

1

shift

4

1101

0000

1

AC=AC+M AC=(AC step3 + M) 0 1

5

1110

1000

0

shift

6

1111

0100

0

shift

Product by Booth’s algorithm= 1111 0100 (-6) x (2) = (-12) +12 = 0000 1100 1111 0011

Q0,Q-1 from step1 = 1 0

AC, Q and Q-1 are shifted to the right by 1 bit.

0 0 1

1 1 0

Q0,Q-1 from step3 = 0 1

1 0 1

Q0,Q-1 from step5 = 0 0

1 1111 0100 Let us perform the multiplication of the given numbers using 5 bits each. Please show the process of multiplication as shown above. a. 510 x 710 b. (-9)10 x 410 Question 5 Study the division method shows below using 6bits (4210) / (610) Dividend divisor 101010 / 000110

divisor

0

0

0

1

1

0 -

1 0 -

0 1 1 0

1 1 0 1

1 0 0 0 1 1 1 0

1 1 1 0 1 1 0

1 0

quotient dividend

0 0 0

= = =

710 4210 610 Let us perform the divis ion of the given

numbers using 6 bits each. Please show the process of division as shown above. c. 5410 / 610 d. 2810 / 410 e. 4610 / 210

Question 6 Study the division steps below.    

 

Step-1: First the registers are initialized with corresponding values (Q = Dividend, M = Divisor, A = 0, n = number of bits in dividend) Step-2: Then the content of register A and Q is shifted left as if they are a single unit Step-3: Then content of register M is subtracted from A and result is stored in A Step-4: Then the most significant bit of the A is checked if it is 0 the least significant bit of Q is set to 1 otherwise if it is 1 the least significant bit of Q is set to 0 and value of register A is restored i.e the value of A before the subtraction with M Step-5: The value of counter n is decremented Step-6: If the value of n becomes zero, we get of the loop otherwise we repeat from step 2



Step-7: Finally, the register Q contain the quotient and A contain remainder

Example 2: Let us perform Division Restoring Algorithm Q - Dividend = (1110) - 10112 D - Divisor = (310) = 000112 N - number of bits in dividend

N 4

3

DIVISO R D

1

QUOTIEN T Q

A

OPERATIONS/STEPS

00011

00000

1011

initialize

00011

00001

011_

shift left AQ

00011

(MSB)

011_

A=A-M (00001 – 00011)

00011

00001

0110(LSB)

If MSB bit of the A is 1 the LSB bit of Q is set to 0 Q[0]=0 And restore A

00011

00010

110_

shift left AQ The value of counter n is decremented

00011

11111

110_

A=A-M (00010 – 00011)

1100

If MSB bit of the A is 1 the LSB bit of Q is set to 0 Q[0]=0 And restore A

00011

2

3

3 11 9 2

11110

00010

00011

00101

100_

shift left AQ The value of counter n is decremented

00011

00010

100_

A=A-M (00101 – 00011)

00011

00010

1001

If MSB bit of the A is 0 the LSB bit of Q is set to 1 Q[0]=1

00011

00101

001_

shift left AQ The value of counter n is decremented

00011

00010

001_

A=A-M (00101- 00011)

00011

00010

0011

If MSB bit of the A is 0 the LSB bit of Q is set to 1 Q[0]=10]=1

Remember to restore the value of A MSB bit of A is 1. As that register Q contain the quotient, 3 and register A contain remainder 2. Let us perform the division of the given numbers following steps given above. Please show the process of division as shown above. f.

1710 / 410

g. 2810 / 610 h. 910 / 210...