Flip Flop MCQ 30June2021 Tutorial PDF

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Summary

Flip Flop MCQ 30 June 2021 !
Contains sample questions on the topic of Flip flops...

Description

1 Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? 2 One example of the use of an S-R flip-flop is as ___________

Gate impedance

Cross coupling

Transition pulse generator Racer

Switch debouncer

Astable oscillator

3 The truth table for an S-R flip-flop has how many VALID entries?

1

3

4

4 Which of the following is correct for a gated D-type flip-flop?

The Q output is either SET or RESET as soon as the D input goes HIGH or LOW AND or OR gates

XOR or XNOR gates

NOR or NAND gates

AND or NOR gates

Combinational circuits

Sequential circuits

Latches

Flip-flops

Set

Reset

Previous state

Current state

5 A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? 6 The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called ________________ 7 In S-R flip-flop, if Q = 0 the output is said to be ___________

Low input voltages

Synchronous operation

2

The output complement Only one of the inputs The output toggles if one of follows the input when can be HIGH at a time the inputs is held HIGH enabled

8 A latch is an example of a ___________

Monostable multivibrator Astable multivibrator

Bistable multivibrator

555 timer

9 Why latches are called memory devices? 10 The full form of SR is ___________

It has capability to store 8 It has internal memory bits of data of 4 bit System rated Set reset

It can store one bit of data Set ready

It can store infinite amount of data Set Rated

11 The SR latch consists of ___________inputs.

1

2

3

4

12 When a high logic is applied to the Set input of an SR latch, then _________ Q output goes high

Q’ output goes high

Q output goes low

Both Q and Q’ go high

13 When both inputs of SR latches are low, the latch ___________

Q output goes high

Q’ output goes high

14 What is an ambiguous condition in a NOR based S-R latch?

S=0, R=1

S=1, R=0

it goes to its next set or It remains in its previously set or reset reset state state S=1, R=1 S=0, R=0

15 What is an ambiguous condition in a NAND based S’-R’ latch?

S’=0, R’=1

S’=1, R’=0

S’=1, R’=1

S’=0, R’=0

16 In a NOR based S-R latch, if S=1 & R=1 then the state of the latch is ______ No change

Set

Reset

Forbidden

17 In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is __ No change

Set

Reset

Forbidden

16 In a NOR based S-R latch, if S=0 & R=0 then the state of the latch is ______ No change

Set

Reset

Forbidden

17 In a NAND based S’-R’ latch, if S’=0 & R’=0 then the state of the latch is ____________

Set

Reset

Forbidden

No change

18 The difference between a flip-flop and latch is ____________

Both are same

19 One example of the use of an S-R flip-flop is as ____________

Racer

20 When is a flip-flop said to be transparent?

When the Q output is opposite the input The clock pulse is LOW

21 On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________ 22 If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________ 23 A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________ 24 How is a J-K flip-flop made to toggle?

Latches has one input Latch has two inputs but but flip-flop has two flip-flop has one Binary storage register Transition pulse generator

SET

When the Q output When you can see follows the input through the IC The clock pulse is HIGH The clock pulse transitions from LOW to HIGH RESET Clear

Invalid

Two AND gates

Two NAND gates

Two NOT gates

Two OR gates

J = 0, K = 0

J = 1, K = 0

J = 0, K = 1

J = 1, K = 1

Constantly HIGH

A 20 kHz square wave A 10 kHz square wave

2

4

16

J-K

T

S-K

The Q output is ALWAYS identical to the CLK input if the D input is HIGH CLK = PGT, D = 0

The Q output is The Q output is ALWAYS ALWAYS identical to identical to the D input the D input when CLK = PGT CLOCK NGT, D = 1 CLOCK PGT, D = 1

S-R flip-flop

T flip-flop

S-K flip-flop J-K, D, T

25 A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output Constantly LOW is ________ 1 26 Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________KHz 27 A D flip-flop can be constructed from an ______ flip-flop. S-R 28 Which statement describes the best, operation of a negative-edge-triggered D flip-flop?

Flip-flop is edge triggered device Stable oscillator

The logic level at the D input is transferred to Q on NGT of CLK

29 A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the CLK = NGT, D = 0 following input actions will cause it to change states? 30 In a J-K flip-flop, if J=K the resulting flip-flop is referred to as ___________ D flip-flop 31 The flip-flops which has not any invalid states are _____________

S-R, J-K, D

S-R, J-K, T

J-K, D, S-R

32 What does the triangle on the clock input of a J-K flip-flop mean?

Level enabled

Edge triggered

33 What does the circle on the clock input of a J-K flip-flop mean?

Level enabled

When the Q output is complementary of the input The clock pulse transitions from HIGH to LOW

Positive edge triggered

Both Level enabled & Level triggered Edge triggered negative edge triggered Level triggered

34 The asynchronous input can be used to set the flip-flop to the ____________ 1 state

0 state

either 1 or 0 state

forbidden State

35 In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

Race around condition

Lock out state

Forbidden State

Conversion condition

36 If one wants to design a binary counter, the preferred type of flip-flop is ___ D type

S-R type

Latch

37 Which of the following flip-flops is free from the race around the problem? T flip-flop

SR flip-flop

38 The term synchronous means ____________

The output changes state The output changes state only when the only when the clock input is triggered input is reversed Synchronous inputs Bidirectional inputs

39 The S-R, J-K and D inputs are called ____________

The output changes state only when any of the input is triggered Asynchronous inputs

J-K type

Master-Slave Flip-flop D flip-flop The output changes state only when the input follows it Unidirectional inputs

40 If one wants to design a register, the preferred type of flip-flop is _________ T type

S-R type

Latch

J-K type

41 The preset,clear inputs are called ____________

Synchronous inputs

Bidirectional inputs

Unidirectional inputs

Asynchronous inputs

42 The time for which input must be stable before PGT clock transition is …..

setup time

hold time

propogation time

delay time

43 The time for which input must be stable from PGTclock transition is …..

setup time

hold time

propogation time

delay time

44 The time required for the output change when input is stable and PGT clock setup time transition is applied ….. Present input 45 The output of the sequential circuit depends upon _________

hold time

propogation time

delay time

Past input

None of the above

46 In which flip flop the present input will be the next output?

S-R

J-K

Present input and present state D

T

47 The preset input is used to make output ______

Q=1

Q=0

Nochange

Invalid

48 The clear input is used to make output ______

Q=1

Q=0

Nochange

Invalid

49 _________ are the applications of flip flop

Registers

Counters

Storage devices

All of these

50 When S=0, R=0, CLK=X then the output will be ___________

Set

Reset

Invalid

No change

51 How many bits of information do flip-flop store?

1 bit

10 bits

2 bits

3 bits...