Ideapad 320-15IKB DG421 DG521 DG721 NM-B242 NM-B241 Rev 1.0 DIS Schematic Diagram PDF

Preview

Summary

Download Ideapad 320-15IKB DG421 DG521 DG721 NM-B242 NM-B241 Rev 1.0 DIS Schematic Diagram PDF

Description

5

4

3

2

1

? SKL_ULT

UC1B 17

DDRA_DQ[0..63]

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

D

C

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

AU53 AT53 AU55 AT55 BA56 BB56 AW56 AY56

17 17

DDRA_CKE0

17

DDRA_CS0#

17

D

AU45 AU43 AT45 AT43 BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR0_MA[3] BB52 DDR0_MA[4] AM70 DDR0_DQSN[0] AM69 DDR0_DQSP[0] AT69 DDR0_DQSN[1] AT70 DDR0_DQSP[1] BA64 DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR0_DQSP[7]/DDR1_DQSP[5] AW50 DDR0_ALERT# AT52 DDR0_PAR AY67 DDR_VREF_CA AY68 DDR0_VREF_DQ BA67 DDR CH - A DDR1_VREF_DQ AW67 DDR_VTT _CNTL

DDRA_CLK0# DDRA_CLK0

DDRA_ODT0

17

DDRA_MA5 DDRA_MA9 DDRA_MA6 DDRA_MA8 DDRA_MA7 DDRA_BG0 DDRA_MA12 DDRA_MA11 DDRA_ACT#

17 17 17 17 17 17 17 17 17

DDRA_MA13 17 DDRA_MA15_CAS# DDRA_MA14_WE# DDRA_MA16_RAS# DDRA_BS0# 17 DDRA_MA2 17 DDRA_BS1# 17 DDRA_MA10 17 DDRA_MA1 17 DDRA_MA0 17 DDRA_MA3 17 DDRA_MA4 17

17 17 17

DDRA_DQS#0 DDRA_DQS0 DDRA_DQS#1 DDRA_DQS1 DDRA_DQS#2 DDRA_DQS2 DDRA_DQS#3 DDRA_DQS3 DDRA_DQS#4 DDRA_DQS4 DDRA_DQS#5 DDRA_DQS5 DDRA_DQS#6 DDRA_DQS6 DDRA_DQS#7 DDRA_DQS7

C

DDRA_DQS#[0..7] DDRA_DQS#[0..7]

17

DDRA_DQS[0..7] DDRA_DQS[0..7]

DDRA_ALERT# 17 DDRA_PAR 17 DDR_SA_VREFCA

17

DDR_SB_VREFCA

18

17

SMVREF WIDTH:20MIL SPACING: 20MIL

DDR_VTT _CNTL

1 OF 20 SKYLAKE-U_BGA1356 REV = 1 @

?

B

B

1

+3VALW

2

RC30 100K_0402_5%

CPU_DRAMPG_CNTL

55

1

+1.2V C

RC3

1 2 1K_0402_5%

2

QC18

B

3

E

MMBT3904W H_SOT323-3

2

DDR_VTT _CNTL

1

RC29 @ 10K_0402_5%

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification 2015/08/20

Deciphered Date

MCP (DDR4)

2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number Custom Date:

5

4

3

2

Re v 1.0

DG421

Sunday, January 22, 2017 1

Sheet

5

of

60

5

4

3

2

1

?

18

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

D

C

SKL_ULT

UC1C

DDRB_DQ[0..63]

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

AN45 AN46 AP45 AP46 AN56 AP55 AN55 AP53 BB42 AY42 BA42 AW42

AY48 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7] DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

DDRB_CLK0# DDRB_CLK1# DDRB_CLK0 DDRB_CLK1

18 18 18 18

DDRB_CKE0 DDRB_CKE1

18 18

DDRB_CS0# DDRB_CS1# DDRB_ODT0 DDRB_ODT1

18 18 18 18

DDRB_MA5 DDRB_MA9 DDRB_MA6 DDRB_MA8 DDRB_MA7 DDRB_BG0 DDRB_MA12 DDRB_MA11 DDRB_ACT# DDRB_BG1

18 18 18 18 18 18 18 18 18 18

DDRB_MA13 18 DDRB_MA15_CAS# DDRB_MA14_WE# DDRB_MA16_RAS# DDRB_BS0# 18 DDRB_MA2 18 DDRB_BS1# 18 DDRB_MA10 18 DDRB_MA1 18 DDRB_MA0 18 DDRB_MA3 18 DDRB_MA4 18

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

DDRB_DQS#0 DDRB_DQS0 DDRB_DQS#1 DDRB_DQS1 DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3 DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#5 DDRB_DQS5 DDRB_DQS#6 DDRB_DQS6 DDRB_DQS#7 DDRB_DQS7

AN43 AP43 AT13 AR18 AT18 AU18

CPU_DRAMRST#_R SM _RCOMP_0 SM _RCOMP_1 SM _RCOMP_2

D

18 18 18

C

DDRB_DQS#[0..7]

DDRB_DQS#[0..7]

18

DDRB_DQS[0..7] DDRB_DQS[0..7]

18

DDRB_ALERT# 18 DDRB_PAR 18 RC24 RC25 RC26

1 1 1

2 121_0402_1% 2 80.6_0402_1% 2 100_0402_1%

DDR CH - B

1 OF 20

SKYLAKE-U_BGA1356 REV = 1

?

@

B

B

1

+1.2V

2

RC22 470_0402_5%

17,18

CPU_DRAMRST#

RC23

1

@

CPU_DRAMRST#_R

2 0_0402_5%

1 CC1 1000P_0201_50V7-K EMC@ 2

A

A

Issued Date

Title

LC Future Center Secret Data

Security Classification 2015/08/20

Deciphered Date

MCP (DDR4)

2016/08/20

THIS SHEET OF ENGINEERI NG DRAW ING I S THE PROPRI ETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORM ATION IT CONTAI NS MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTUR E CENTER.

Size Document Number Custom Da te:

5

4

3

2

R ev 1.0

DG421 Sh eet

Sunday, January 22, 2017 1

6

of

60

5

4

3

2

1

+3VALW_PCH

+3VS

+3VS

?

44

SPI_SO

44

SPI_SI

44

SPI_CS0#

SPI_SI SPI_CS0#

RC52

1

RC51

1

@

2 15_0402_5%

SPI_SI_R

2 0_0402_5%

SPI_CS0#_R

AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

3 4 SMBUS, SMLINK

GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT#

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

W3 GPP_C6/SML1CLK V3 GPP_C7/SML1DATA AM7 GPP_B23/SML1ALERT#/PCHHOT#

SPI - TOUCH

8

BOARD_ID4

BOARD_ID4

M2 M3 J4 V1 V2 M1

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

44

KBRST#

32,44

SERIRQ

KBRST# SERIRQ

AW13 AY11

PCH_SMB_CLK PCH_SMB_DATA SMB_ALERT#

RPC20 2.2K_0404_4P2R_5%

DIMM, NGFF

SML0_CLK SML0_DATA SML0_ALERT# PCH_SML1_CLK PCH_SML1_DAT SML1_ALERT#

PCH_SMB_CLK

QC2A

RPC24

D

2.2K_0404_4P2R_5%

6

1

SMB_CLK_S3

18,40

2N7002KDW H_SOT363-6

GPU, EC, Thermal Sensor PCH_SMB_DATA

QC2B

3

4

SMB_DATA_S3

18,40

2N7002KDW H_SOT363-6 LPC

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET#

C LINK

G3 G2 G1

R7 R8 R10

R9 GPP_C3/SML0CLK W2 GPP_C4/SML0DATA W1 GPP_C5/SML0ALERT#

1 2

SPI_CLK_R SPI_SO_R SPI_SI_R SPI_WP#_R SPI_HOLD#_R SPI_CS0#_R

5

SPI_SO_R

G

2 15_0402_5%

S

SPI_CLK_R

1

D

2 15_0402_5%

RC53

2

RC1539 1

SPI_SO

G

SPI_CLK SPI_CLK

S

44

D

D

2 1

SPI - FLASH

4 3

SKL_ ULT

UC1E

CL_CLK CL_DATA CL_RST#

AY13 BA13 BB13 AY12 BA12 BA11

AW9 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 GPP_A10/CLKOUT_LPC1 AW11 GPP_A8/CLKRUN#

GPP_A0/RCIN# GPP_A6/SERIRQ

SUS_STAT#

LPC_AD0 32,44 LPC_AD1 32,44 LPC_AD2 32,44 LPC_AD3 32,44 LPC_FRAME# 32,44

1 TC81@

CLK_PCI _EC_R CLK_PCI _TPM_R PM_CLKRUN#

RC173 2 RC1541 2 TPM@

1 22_0402_5% 1 22_0402_5%

CLK_PCI_EC CLK_PCI _TPM PM_CLKRUN#

44 32 32

1 OF 20

SKYLAKE-U_BGA1356 REV = 1

?

@

+3V_SPI C

C

+3VS

+3VALW_PCH

+3VS

check CLKRUN# / SUS_STAT# signal if need to connect

RC171

1

@

2 0_0402_5%

RC172

1

@

2 0_0402_5%

+3VALW_PCH PM_CLKRUN#

RC11

1

2 8.2K_0402_5%

SERIRQ

RC12

1

2 10K_0402_5%

KBRST#

RC10

1

KBRST#

CC1255

SMB_ALERT#

2

SML0_CLK SML0_DATA

4 3

+3V_SPI

*

1. If support DS3, connect to +3VS and don't support EC mirror code; 2. If don't support DS3, connect to +3VALW _PCH and support EC mirror c ode.

2

+3VALW_PCH

1000P_0201_50V7-K

RPC23

1 2

2.2K_0404_4P2R_5%

+3VALW_PCH

1

1

RC1562

2 10K_0402_5%

1

EMC_NS@

+3V_SPI

1 2.2K_0402_5%

RC60 1K_0402_5%

RC61 1K_0402_5%

SML0_ALERT#

RC1564 2

@

1 2.2K_0402_5%

SPI_WP#_R

RC54

1

@

2

15_0402_5%

RC55

1

@

2

15_0402_5%

SPI_WP#

+3VALW_PCH

This si gnal has a w eak internal pull-down. 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC. Notes: 1. The internal pull-down is disabled after RSMR ST# de-ass e rts. 2. This si gnal is in the primary wel Rising edge of RSMRST#

+3VS

SPI_HOLD#

4 3

SPI_HOLD#_R

2

2

Check with BIOS, SPI is Dual mode or quad mode

G

2

RPC25 2.2K_0404_4P2R_5%

B

+3VALW_PCH

1 2

B

QC10A

6

1 @

EC_SMB_CK2

D

PCH_SML1_CLK

S

+3V_SPI

4

/CS

VCC

DO (IO1)

IO3

IO2 GND

CLK DI (IO0)

8 7

SPI_HOLD#

6

SPI_CLK

5

RC1569 1 RC1655 1

@

+3VS

2 150K_0402_5% 2 150K_0402_5%

G

3

1

CC8 0.1u_0201_10V6K

PCH_SML1_DAT

QC10B

3

4

S

2

SPI_WP#

@

D

1

SPI_SO

5

2N7002KDW H_SOT363-6

UC3

SPI_CS0#

SML1_ALERT#

20,39, 44

SPI_SI

2

EC_SMB_DA2

To enable Direct C onnect Interface (DC I), a 150K pull up resistor w ill need to be added to PCHHOT# pin. This pin must be low during the risi ng edge of RSMRST#. (Refer to WW52_MOW)

20,39, 44

2N7002KDW H_SOT363-6

W 25Q64JVSSI Q_SO8

A

A

Issued Date

Title

LC Fu ture Cen ter Secret Da ta Data

Security Classification 2015/08/20

Deciphered Date

MCP (MISC,JTAG,SPI,LPC,SMB) I,L

2016/08/20

CONTAINS CONFIDEN TIAL THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS NOT BE FROM THE DIVISION OF AND TRADE SECR ET IN FORMATION. TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D THE IN FORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTUR E CENTER NEITHER THIS SHEET NOR THE MAY BE USED BY OR DISCL OSED TO ANY THIRD PARTY W ITHOUT PRIOR WR ITTE...