Questionaire 3 - P5 P6 P7 P8 projects PDF

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8/5/2018

(3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

CAMPUS VIRTUAL UPC  My courses  2017/18-02:EETAC-300022-CUTotal  (3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

Started on

 CSD

Tuesday, 8 May 2018, 9:30 AM

State Finished Completed on Time taken

Tuesday, 8 May 2018, 9:55 AM 24 mins 47 secs

Grade 5.00 out of 10.00 (50%) Question 1 Correct Mark 1.00 out of 1.00

With respect to the Counter_mod16 in the picture below, which is the next state after the CLK's rising edge?

Select one: a.

"1001", because the system is disabled or inhibited

b.

"1100"

c.

"1011"

d.

"1000"

Your answer is correct. The correct answer is:

"1000"

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(3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

Question 2 Incorrect Mark 0.00 out of 1.00

The schematic below represents the internal architecture of a FSM to control a traffic light system. 6 outputs drive the coloured lamps and 6 inputs from several sensors and buttons determine how the machine works. The FSM has 5 states and they are coded in one-hot. Which one is the right answer?

Select one: a.

The state register contains 5 DFF; CC1 is a truth table that contains 512 combinations;

CC2 has a truth table that contains 64 combinations. b. The state register contains 3 DFF; CC1 is a truth table that contains 512 combinations; CC2 has a truth table that contains 8 combinations c.

The state register contains 5 DFF; CC1 is a truth table that contains 2048

combinations; CC2 has a truth table that contains 32 combinations. d. It is not possible to encode the machine using one-hot code (00001, 00010, 00100, 01000, 10000) because binary sequential is required (000, 001, 010, 011, 100, 101).

Your answer is incorrect. The correct answer is: The state register contains 5 DFF; CC1 is a truth table that contains 2048 combinations; CC2 has a truth table that contains 32 combinations.

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(3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

Question 3 Correct Mark 1.00 out of 1.00

Using and interconnecting 3 universal counters modulo 10 (Counter_mod10) like the one depicted below and other components like logic gates, we can design many different counters. Which is the maximum modulo that can be attained when connected in cascade?

Select one: a.

Counter_mod100

b.

Counter_mod300

c.

Counter_mod30

d.

Counter_mod1000

Your answer is correct. The correct answer is:

Counter_mod1000

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(3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

Question 4 Correct Mark 1.00 out of 1.00

The following figure shows the logic diagram of a presettable synchronous up/down binary counter. Indicate the number of states of the counter and justify your response.

Select one: a. 16 b. 4 c. 8 d. 2

Your answer is correct. The correct answer is: 16

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Question 5 Incorrect Mark 0.00 out of 1.00

The picture is the top view of a 74LS76A, a chip that contains individual JK flip flops with set direct (SD, PRE_L) an clear direct (CD, CLR_L) signals. Deduce the the voltage level that activates the asynchronous signals and the number of JK flip flops included in the chip.

Select one: a.

Low level, 1

b.

Low level, 2

c.

High level, 2

d.

High level, 1

Your answer is incorrect. The correct answer is:

Low level, 2

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(3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

Question 6 Incorrect Mark 0.00 out of 1.00

A CLK_generator circuit is designed cascading frequency dividers and a T_FF as shown in the picture. Which is the frequency of the output port CLK_n_SQ if the input CLK frequency is 10 MHz?

Select one: a.

25 kHz

b.

250 kHz

c.

12.5 kHz

d.

250 Hz

Your answer is incorrect. The correct answer is:

12.5 kHz

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Question 7 Correct Mark 1.00 out of 1.00

Which is the correct output of this JK flip flop connected as shown in this schematic?

Select one: 1.

Waveforms b)

2.

Waveforms d)

3.

Waveforms c)

4.

Waveforms a)

Your answer is correct. The correct answer is:

Waveforms b)

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Question 8 Incorrect Mark 0.00 out of 1.00

The state diagram below corresponds to a FSM of a given application. State transitions are represented by arrows. The outputs of the system are written in parenthesis and using a different colour. Which one is the right answer?

Select one: a.

The states can be coded in binary sequential requiring only 3 DFF in the state register

process. b.

The initial sate of the system after asserting CD cannot be the state labelled as "rowa".

c.

A simple 3-bit up counter can solve the FSM.

d.

The states can be coded in one-hot requiring up to 7 DFF in the state register process.

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(3GM1) Questionaire #3 - P5 / P6 / P7 / P8 projects

Your answer is incorrect. The correct answer is:

The states can be coded in binary sequential requiring only 3 DFF in the

state register process.

Question 9 Incorrect Mark 0.00 out of 1.00

This is a schematic copied from the book T. L. Floyd, Digital Fundamentals, 9th ed., Prentice Hall, 2006. It is a design of a real-time clock that has HH:MM:SS BCD outputs. The names of the components and signals has not been adapted to our CSD naming style, but they are very similar. The wave-shaping circuit is analogue. The question, after inspecting the circuit, is: how many D-FF it contains?

Select one: a.

The circuit contains 59 data registers D-FF

b.

The circuit contains 14 data registers D-FF

c.

The circuit contains 192 data registers D-FF

d.

The circuit contains 26 data registers D-FF

Your answer is incorrect. The correct answer is:

The circuit contains 26 data registers D-FF

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Question 10 Correct Mark 1.00 out of 1.00

A toggle flip flop (TFF) is connected as shown in the picture. The the output frequency.

period is 5 ms. Indicate

Select one: a.

100 Hz

b.

50 Hz

c.

200 Hz

d.

Q = '0' and there is no waveform

Your answer is correct. The correct answer is:

100 Hz

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