Unit 4 - Input/Output organization : Input interface Data transfer techniques : synchronous PDF

Title Unit 4 - Input/Output organization : Input interface Data transfer techniques : synchronous
Author POLI POLI
Course Computer Organisation and Assembly Language Programming
Institution Pondicherry University
Pages 11
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Summary

Input/Output organization : Input interface Data transfer techniques : synchronous
asynchronous
Interrupt driven
Intel 8086/88 interrupt organization
types
DMA
I/O processors serial communication...


Description

UNIT IV INPUT/OUTPUT ORGANIZATION I/O Modules: External devices are not generally connected directly into the bus structure of the computer – Wide variety of devices require different logic interfaces -- impractical to expect CPU to ―know how‖ to control each device – Mismatch of data rates – Different data representations The I/O module – Provides a standard interface to the CPU and the bus – Tailored to specific I/O device and its interface requirements – Relieves the CPU of the management of the I/O devices – Interface consists of  » Control  » Status and  » Data signals

I/O Module block diagram Programmed I/O: I/O operation in which CPU issues the I/O command to the I/O module CPU is in direct control of the operation – CPU waits until the I/O operation is completed before it can perform other tasks – Completion indicated by a change in the module status bits – CPU must periodically poll the module to check its status

As a result of the speed difference between a CPU and the peripheral devices (orders of magnitude), programmed I/O wastes an enormous amount of CPU processing power – Very inefficient – CPU slowed to the speed of the peripheral Advantages – Simple to implement – Requires very little special software or Hardware

Programmed I/O operation: I/O addressing – Isolated (standard) I/O  » Address space of the I/O modules is isolated from the memory address space  » Separate instructions in the instruction set are used to perform I/O  » Typical control lines include the read/write lines plus an IO/M line to switch address reference between memory space and I/O space – Memory mapped I/O  » I/O devices are integrated into the normal memory address space  » All of the memory accessing instructions can be used to access the I/O peripherals



» ―Cost‖ is the loss of ―real‖ memory addresses Not a big problem today with the huge address spaces in current systems

DATA TRANSFER TECHNIQUES Synchronous and Asynchronous: Interface usually has 2 types of signals: o Data signals (the "information") o Control signals: synchronization Transfer of Data may be Synchronous or Asynchronous SYNCHRONOUS Transmission o Data transfer Synchronized to a Clock signal o Transfer rate is limited by speed of Clock ASYNCHRONOUS Transmission o No Clock - Data transfer controlled by logic signals (e.g. Strobe/Acknowledge) o Transfer rate limited by speed of devices Both Parallel and Serial interfaces may be Synchronous or Asynchronous SYNCHRONOUS: Regular. Most communication within a computer system is synchronous, controlled by the computer's own internal clock, while communication between computers is usually asynchronous. Synchronous telecommunications are, however, becoming more widely used. ASYNCHRONOUS: Irregular or not synchronised. In computer communications, the term is usually applied to data transmitted irregularly rather than as a steady stream. Asynchronous communication uses start bits and stop bits to indicate the beginning and end of each data block.

Interrupt driven: Interrupt-Driven I/O: The CPU can use an interrupt-driven approach  CPU issues I/O command to the module  CPU continues with its other tasks while the module performs its task  Module signals the CPU when the I/O operation is finished (the interrupt)  CPU responds to the interrupt by executing an interrupt service routine and then continues on with its primary task CPU recognizes and responds to interrupts at the end of an instruction execution cycle Interrupt technique is used to support a wide variety of devices

Interrupt-driven I/O







CPU’s response to an interrupt Design issues -- with multiple modules and thus multiple interrupts How does the CPU determine which device caused the interrupt? If multiple interrupts occur at the same time, which is processed first? Interrupt determination Provide multiple interrupt signal lines for a system o » Practical only for small numbers of interrupts Use 1 interrupt for more than 1 device o » Must perform some sort of device polling to determine which requested service o » Requesting device can place an ID on the bus -vectored interrupts o » Bus arbitration and vectored interrupts Determination scheme prioritizes multiple interrupts

Interrupt Controller

DMA: Both programmed and interrupt driven I/O require the continued involvement of the CPU in ongoing I/O operations Direct memory accessing takes the CPU out of the task except for initialization of the operation Large amounts of data can be transferred between memory and the peripheral w/o severely impacting CPU performance – CPU initializes DMA module  » Read or write operation defined  » I/O device involved  » Starting address of memory block  » Number of words to be transferred – CPU then continues with other work

DMA operates by ―stealing‖ bus cycles from the CPU – In practice, it uses the bus when the CPU is not using it -- no impact on the CPU performance – Accesses memory to retrieve a data word – Forwards the word to the I/O peripheral

DMA configurations

I/O processors: All about I/O: Computers aren't useful unless we can put data into them, and get results out. input -- data to computer output -- data from computer computer model: -----------|CPU| |memory| ----- ^ -------| | \/ ----|i/o| -----

Examples of input devices: keyboard, mouse, network, disk, etc. Examples of output devices: printer, (terminal) display, network, etc. Simulator has only 2 I/O devices,  Keyboard (for input)  display (for output) Issues that must be solved: Programmer interface -- tools give get_ch, put_ch, put_str These are actually OS implemented procedures. (The OS is the program that interfaces between the programmer or application user and the actual hardware. For us, it is NT.) Protection issues -- in a real system, there could be more than one terminal (terminal is a keyboard and display together) Physical issues --A computer today (1998) can complete an instruction at the rate of about 1 each nsec. Unfortunately, typical I/O devices are much slower, often requiring 10s of milliseconds to deal with a single character. That is approx. 1 million times slower! This situation is dubbed the "access gap." Disk - a real, live, physical device PLATTER -- sort of like a phonograph record or CD. Data is stored on a SURFACE of a platter. All platters are tied together and rotate around the SPINDLE at a fixed speed. Each surface has one or more READ/WRITE HEADS. Platters are broken down into TRACKS. A single track is one of many concentric circles on the platter. All the corresponding tracks on all surfaces, taken together, form a CYLINDER. Each track is broken down into SECTORS. How we read/write to a sector. Given: the sector position on the cylinder. (looked up in a table, or calculated from the disk address). -- the disk is spinning. -- the read/write head is moving to the correct cylinder (track). THIS TAKES A LONG TIME RELATIVE TO THE OTHER STUFF. It is the physical movement, acceleration, etc. comes into play. This is SEEK time. -- once the read/write head is over the correct cylinder, there is bound to be some time to wait until the correct sector is under the head. This is ROTATIONAL LATENCY. -- Even at the correct sector, it still takes some time for the data to be read/written. This is the READ or WRITE time. Time to read a sector = seek time + rotate time + read time. So, the nitty gritty issue is: how does the OS accomplish I/O requests? There are 2 possibilities. 1. have special I/O instructions -- input need to know which device, how much data, where the data is to go -- output need to know which device, how much data, where the data currently is How does the processor know that the instruction has completed? (Is there any need to wait?)

What happens if the device encounters an error? (Does this halt the computer?) 2. the solution of choice overload memory locations to use as communication channels. for example, address 0x0000 0000 -| . | real memory . | . | 0xffff 0000 -| 0xffff 0008 - data from keyboard (Keyboard_Data) 0xffff 0010 - data to display (Display_Data) then, by reading (loading) from location 0xffff0008, data is requested from the keyboard then, by writing (storing) to location 0xffff0010, data is sent to the display the syscall code in the OS must be (in essence) mov eax, Keyboard_Data # get_ch syscall return from syscall and mov Display_Data, eax # put_ch syscall return from syscall This method of I/O is called MEMORY-MAPPED I/O. Problems with memory-mapped I/O as currently given: -- get_ch presumably returns once a character has been typed. What happens if the user does not type a character?Types it on the wrong keyboard? Goes to get a drink of water? What happens to the data if the user types 2 characters before get_ch has been called? How does the computer know if a character has been typed? -- put_ch and put_str: how does the computer know that the device is ready to print out a second character? What if the printer jams? (printers and terminals are SLOW!) What is needed is a way to convey information about the STATUS of I/O devices. This status information is used to coordinate and SYNCHRONIZE the useage of devices. address 0x0000 0000 -| . | real memory . | . | 0xffff 0000 -| 0xffff 0008 - data from keyboard (Keyboard_Data) 0xffff 000c - STATUS from keyboard (Keyboard_Status) 0xffff 0010 - data to display (Display_Data) 0xffff 0014 - STATUS from display (Display_Status)

Serial communication: In telecommunications and computer science, serial communications is the process of sending data one bit at one time, sequentially, over a communications channel or computer bus. This is in contrast to parallel communications, where all the bits of each symbol are sent together. Serial communications is used for all long-haul communications and most computer networks, where the cost of cable and synchronization difficulties make parallel communications impractical. Serial computer buses are becoming more common as improved technology enables them to transfer data at higher speeds. Teletype systems: Standard teletype systems evolved as an automated telegraphy system called telex. Originally, a rotating mechanical commutator (a rotating switch) was started by a "start bit". The commutator would distribute the other bits to set relays that would pull on solenoids which would cause the mechanism to print a figure on paper. The routing was automated with rotary electromechanical dialing systems like those used in early telephone systems. When computers became commonplace, these serial communication systems were adapted using I/O devices called serial ports that used UARTs. The development of communications hardware had a deep continuing impact on the nature of software and operating systems, both of which usually arrange data as sequences of characters. Serial buses: Integrated circuits are more expensive when they have more pins. To reduce the pins, many ICs use a serial bus to transfer data when speed is not important. Some examples of such low-cost serial buses include SPI, I²C, and 1-Wire. Serial versus parallel: The communications links across which computers—or parts of computers—talk to one another may be either serial or parallel. A parallel link transmits several streams of data (perhaps representing particular bits of a stream of bytes) along multiple channels (wires, printed circuit tracks, optical fibres, etc.); a serial link transmits a single stream of data. At first sight it would seem that a serial link must be inferior to a parallel one, because it can transmit less data on each clock tick. However, it is often the case that serial links can be clocked considerably faster than parallel links, and achieves a higher data rate. A number of factors allow serial to be clocked at a greater rate: Clock skew between different channels is not an issue (for unclocked serial links): A serial connection requires fewer interconnecting cables (e.g. wires/fibres) and hence occupies less space. The extra space allows for better isolation of the channel from its surroundings Crosstalk is less of an issue, because there are fewer conductors in proximity. In many cases, serial is a better option because it is cheaper to implement. Many ICs have serial interfaces, as opposed to parallel ones, so that they have fewer pins and are therefore cheaper....


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