Designing Different types of Counters in Logisim. PDF

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Designing Different types of Counters in Logisim. Asynchronous 4-bit Up and Down Counter, Synchronous 4-bit Up and Down Counter using Logisim...

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LINEAR INTEGRA TED CIRCUITS

Experiment Name: Asynchronous and Synchronous Up-Down Counter Using J-K flip-flop Objectives: 1. To know about counters and its various types. 2. To design different types of counters using LOGISIM. 3. Testing the output of the counters according to the truth table. Introduction: Counter is a sequential circuit which can store and display how many times an event or process has occurred. It is designed by cascading a number of flip flops and a clock as an input to implement the storing action. There are two types of counters: 1. Asynchronous Counters 2. Synchronous Counters Asynchronous counters are those whose output is free from the clock signal. In this type of counter, the clock input is connected to first flip flop and the other flip flops in counter receive the clock signal input from Q’ output of previous flip flop.

Fig 1: Circuit Diagram of a 4-bit Asynchronous “UP” Counter

Fig 2: Signal diagram of an Asynchronous counter The first flip flop has a positive-edge triggered clock input, so it toggles with each rising edge of the clock signal. The other flip flops using the output of the first flip flop has a negative-edge triggered clock input, so they toggle with each falling edge of the preceding flip flop. Synchronous counters are those whose output is dependent on the clock signal. The clock input of all the individual flip-flops within the counter are all clocked together at the same time by the same clock signal. Fig 3: Circuit Diagram of a 4-bit Synchronous counter

Fig 4: Signal Diagram of a 4-bit Synchronous counter Implementation of 4-bit Asynchronous Counter using LOGISIM

Implementation of 4-bit Synchronous Counter Using LOGISIM

Conclusion: Designing the counter circuits in Logisim needs proper attention as the connections can go wrong or remain unconnected. Selection of the proper component from the component tree of the Logisim was made perfectly. The wiring of the circuit was taken good care and rechecked. The i/o bits of each component was preserved correctly as the circuit need. The functionality and the simulation of the circuits were as expected. Asynchronous Counters can give propagation delay if the clock frequency goes high. The truth table of the input clock pulse and the outputs was matched undoubtedly with the circuit designed. Finally, the objectives of the experiment were fulfilled....