ECE 112 Laboratory #7 PDF

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ECE 112 Laboratory #7...

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Lab 7: Multisim Timing and Hazards Friday 2:00 – 5:00 Lab 3/30/2018

Abstract: This laboratory experiment explores the delays in signal propagation from a source through an array of logic gates—that is, the basic hardware components that make up computers —and considers the potential implications of these delays. In particular, it focuses on how adding more or fewer gates can affect the output signal. These experiments are conducted using a computer program called Multisim to simulate the circuits that would be built. Throughout the entirety of the lab, six separate circuit designs were created and analyzed. In each case, the signal of the output was measured and compared with that of the input with respect to time. Overall, we noticed that there was a delay between the two signals, proving that no matter how fast electricity might flow, it can never “turn on” instantaneously. Delays of approximately 20 nanoseconds were noted, and graphically it became visible how this delay could cause an error in the output signal. For each of the circuit designs, this error came in the form of an irregular blinking light, but if this type of error were to occur in a much more complicated computing system, it could cause severe systems failures. For example, your computer might return incorrect results. The method for combatting this failure is to add additional logic gates, however this has the added downside of being significantly less efficient.

Part 1: We began the first part of this lab by familiarizing ourselves with NI Multisim—a computer simulation program used to module circuits and simulate their behavior. Through trial and error, we figured out how to use the program, and eventually came up with our first circuit, as appears below:

Figure 1: Our first circuit design

We used switches to control the inputs of the gates, and then connected the outputs to LEDs in order to better see the output values (meaning the LED would light up for a one or stay dark for a zero). The truth table for the circuit is as follows:

Switches:

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 3 4 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Table 1: Truth table for our first circuit

5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Output 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1

Next, we selected a combination of two sets of inputs that would result in a change in output. Basically, we wanted to observe the output change from zero to one. We choose minterms 11111 and 00000 as our input combinations, because these would give us a change in output. For our next step, we would analyze the results of these changes. To do this, we connected a signal

generator with a step function output to all of our switches. By doing this, the input will vary from 00000 to 11111 every second. Next, we observed the output using an oscilloscope and zoomed in very close at the point where the input and output changes. Our result can be seen below:

Figure 2: Graph of signals from first circuit As can be observed on the graph, there is approximately a 50 ns delay on the output. Having completed our construction and analyzation of the first circuit, we moved on to our second circuit design. We essentially repeated the same process over again, starting with the initial circuit construction:

Figure 3: Our second circuit design

As we quickly discovered, the truth table of the output for our new circuit design is identical to the previous circuit. Once again, we used a function generator and the oscilloscope to observe the signals produced at the output. The timing diagram was as follows: As visible from the diagram, the time delay was about 20 ns, which is significantly lower than our previous circuit. Finally, for the last section of part one of the lab we constructed a K–map using our truth table and simplified the circuit to its minimal equivalent:

Figure 4: Timing diagram for our second circuit

Figure 5: Our K-map for circuit designs one and two

We then constructed this optimized equivalent circuit, and analyzed it as we had for all the others with a function generator and oscilloscope:

Figure 7: Timing diagram for optimized circuit

As shown in the timing diagram, there is a significant increase in the time delay from the input to the output. However, the gate cost significantly less. While it should be noted that it is possible to reduce the cost of the first two circuits, it is important to keep in mind that when designing circuits, there’s always a tradeoff between a cost-efficient circuit versus a more accurate circuit. Ultimately, it depends on the function that this circuit will be implementing. In

some cases, a less accurate circuit may work fine, though generally accuracy is probably better than worrying about the cost.

Part 2: In the second part of this lab, we built two circuits that were significantly more complicated, as they required two outputs. Following a similar procedure as part one, we first built and then analyzed the performance of these circuits. Our first circuit and its truth table are as follows

Figure 8: Our first circuit design

X1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

X2 X3 X4 F 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 Table 2: Truth table for our first circuit

G 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0

To best analyze the change of the output, we chose minterms 0000 and 0101, since both the outputs changed moving from one minterm to the other. The timing diagram of LED1 is as follows:

The timing diagram for the LED2 is as follows:

Figure 10: Timing diagram for LED2

We could not find a true value for the delay for the output since the signal generator did not yield a signal that we could properly analyze for delays (notice the slant at the crossing point of the two signals; when zoomed in very close, the slanted signal becomes flat). For the next step, we continued by building our second circuit, which is as follows:

Once again, the truth table of this circuit is identical to the previous circuit. However, our timing diagram for LED1 a bit different:

Figure 12: Timing diagram for LED1

The time delay is roughly about 75 ns. The timing diagram for LED2 yielded a time delay of roughly 50 ns, as can be observed below:

Figure 13: Timing diagram for LED2

As is quite clearly observable, the timing delay is significantly lower in the second circuit design. We were unsure of the reason behind this difference, though our guess was that NOR gates require less transistors to operate, and therefore have a significantly lower time delay. In the final stage of this section of the lab, we reduced the circuits down to an optimized form. We realized that the outputs could be simplified using the assistance of the following Kmaps:

Figure 14: K-maps for output functions 1 and 2

Notice that the K-map for the second LED can be built into circuit much easily if a product of sum is used. Following the results of our K-map, we modified the circuit to look like the following:

Figure 15: Our optimized circuit design Once again measuring the effect of this circuit, we observed the following timing diagram:

Figure 16: Timing diagram for LED1

This time delay was about 90 ns. The timing diagram for the second LED is as follows:

Figure 17: Timing diagram for LED2

Once again, the time delay is about 90 ns. Surprisingly, the time delay is higher than the circuit in figure 11. This further proves our hypothesis regarding NOR and NAND gates having less transistors. Despite the reduction of gates, the time delay is much higher. Cost wise, having less gates is better. But performance wise, the same may not be true.

Part 3: In the final part of this lab, we began our experiments by building the following circuit:

Figure 18: Our first circuit design Then we constructed the following truth table: x

y 0 0 0 0 1 1 1 1

Out

z 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 0 0 1 1 1

Figure 19: Truth table for the first circuit design

Our next step was to work out the K-Map of the circuit and try to predict the hazards in the system. The K-Map is as follows

Figure 20: K-map for the first circuit design

As indicated on the K-map, there should be a hazard when translating from 110 to 111. With this in mind, built our circuit and observed the following time diagram:

Figure 21: Timing diagram of the first circuit

As is clearly visible in the timing diagram, there is a hazard in the circuit. To fix it, we would need to include the term xy in our expression (shown as AB in the diagram).

The new expression then becomes: F = AB + BC’+AC Thus, our new circuit will become the following:

Figure 22: New circuit design without hazards

After examining the timing diagram, we noticed we had successfully eliminated the hazard:

Figure 23: Timing diagram for new circuit...